Altera LVDS SERDES Transmitter / Receiver - Manual (Page 17)

Table 6: ALTLVDS_RX Parameter Settings
Option Description
General (page 3)
Implement Deserializer circuitry in
logic cells
Turn on this option to implement the SERDES circuitry in
logic cells. The receiver starts its operation on the first fast clock
edge after the PLL is locked. This option is intended for slow
speeds. The byte alignment may be different from the hard
SERDES implementation. Turn off this option to use the
dedicated SERDES circuitry in the device.
This option is supported in Arria GX, Arria II GX, Arria II GZ,
HardCopy II, HardCopy III, HardCopy IV, Stratix, Stratix GX,
Stratix II, Stratix II GX, Stratix III, and Stratix IV devices. In
Cyclone series, except Cyclone V devices, the SERDES is always
implemented in logic cells. Cyclone V devices contain
dedicated SERDES circuitry.
Enable Dynamic Phase Alignment
mode
Turn on this option to correct the skews created by the
different trace lengths on the data channels routed to the
device. This mode adds several ports and parameters to the IP
core instances.
This option is available for Arria GX, Arria II GX, Arria II GZ,
Arria V, Arria V GZ, HardCopy II, HardCopy III, HardCopy
IV, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III,
Stratix IV, and Stratix V devices only.
Enabling the DPA mode changes the appearance of the graphic
representation of the IP core in the left-hand pane. When you
turn on the DPA mode, additional ports and parameters are
added to the IP core. Depending on the selected device, the
following pages are added to the parameter editor to include
the additional DPA mode settings:
• DPA settings 1
• DPA settings 2
• DPA settings 3
What is the number of channels? The number DPA settings 3of input channels available for the
LVDS receiver.
If the required number of channels is not available in the list,
type the desired number in this box. For example, if the
number of channels is 44, the port created is
tx_out[43..0]
.
The legal values depend on the pins available in the device. For
the legal values available for your device, refer to the relevant
device handbook.
UG-MF9504
2014.12.15
ALTLVDS_RX Parameter Settings 17
LVDS SERDES Transmitter/Receiver IP Cores User Guide Altera Corporation
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