Altera LVDS SERDES Transmitter / Receiver User Manual
Page 13
Option
Description
Use 'tx_pll_enable' input port
Turn on to control the enable port of the fast PLL that the IP
core uses with this function.
If the transmitter shares the PLL with other ALTLVDS blocks,
and uses the
tx_pll_enable
port, you must use this port in all
the IP core instances and tie the signals together in the design
file. If you use a PLL-enabled port in one IP core instance and
not another, the PLLs are not shared, and a warning appears
during compilation.
Use 'pll_areset' input port
Turn on to control the asynchronous reset port of the PLL that
the IP core uses with this function.
When the transmitter shares the PLL with other ALTLVDS
blocks and uses the
pll_areset
port, you must use this port in
all the IP core instances and tie the signals together in the
design file. If you use the
pll_areset
port in one IP core
instance only, the PLLs are not shared and a warning appears
during compilation.
The PLL must be reset to set the output clock phase relation‐
ships correctly when the PLL loses lock, or if the PLL input
reference clock is not stable when the device completes the
configuration process.
Align clock to center of data window
Turn on this option to add a phase shift of 90° to the clock,
which center-aligns the clock in the data. Turn on this option
for PLL merging if you also turn on this option for the receiver.
This option is available only for Arria GX, Stratix II, Stratix II
GX, and HardCopy II devices when you implement the
SERDES in logic cells, and for Cyclone II devices.
Enable self-reset on lost lock in PLL
Turn on this option to reset the PLL automatically whenever
the PLL loses lock.
This option is available only for Arria II GX, Arria II GZ,
HardCopy III, HardCopy IV, Stratix III, and Stratix IV devices
when SERDES is implemented in logic cells, and for Cyclone lll
and Cyclone lV devices.
Use shared PLL(s) for receivers and
transmitters
Turn on this option for your LVDS receivers and transmitters
to share the same PLL.
Turn on this option if the LVDS receivers and transmitters use
the same input clock frequency, deserialization factor, and data
rates.
UG-MF9504
2014.12.15
ALTLVDS_TX Parameter Settings
13
LVDS SERDES Transmitter/Receiver IP Cores User Guide
Altera Corporation