Altera LVDS SERDES Transmitter / Receiver - Manual (Page 51)

1. The following events occur during the DPA calibration process:
2. The ALTLVDS_RX IP core counts 256 data transitions, then inserts delay elements on the LVDS
receiver data path to skew the clock and data relationship.
3. The ALTLVDS_RX IP core counts 256 data transitions, then removes the delay elements on the LVDS
receiver data path, restoring the original clock to data relationship.
4. The ALTLVDS_RX IP core counts 256 data transitions, and then asserts the
rx_dpa_locked
signal.
With the Stratix IV production devices, you can choose to use the DPA PLL calibration method to be
backward compatible with Stratix III and Stratix IV ES devices by turning on Enable PLL calibration in
the ALTLVDS_RX parameter editor. If you turn off Enable PLL calibration in the ALTLVDS_RX
parameter editor, the receiver IP core uses delay elements in the receiver data path.
Arria II devices always use the DPA calibration method using delay elements in the receiver data path.
Effects of DPA PLL Calibration
There are two notable effects when DPA PLL calibration is enabled: effect on the timing of the logic
clocked by the PLL, and effect related to the merging PLLs.
During PLL phase calibration, the I/O timing is pulled in by quarter of the voltage-controlled oscillator
(VCO) period. All outputs of the PLL, including the slow clock, are affected. All HSIO TX data from
interfaces, clocked by the affected PLL, clocks out quarter of the VCO period earlier. Likewise, all HSIO
RX data clocks quarter cycle out of phase with the VCO but has less time to be sampled. For the slow
clock that drives the core and the system, there is a loss of quarter of the VCO period on internal timing,
across clock domain transfers in the core. The quarter period-pull greatly affects a design that has cross-
clock transfer without using a FIFO, and the two clocks are not from the same PLL.
If DPA PLL calibration is enabled, PLLs, between receiver and transmitter instances or multiple receiver
instances, do not merge even if the Share PLLs for receivers and transmitters setting is enabled. To force
merging of such PLLs, use
FORCE_MERGE_PLLS=ON
setting in the Quartus II Settings File (.qsf).
Related Information
Quartus II Settings File Manual
Initialization and Reset
This section describes the initialization and reset aspects, using control characters. This section also
provides a recommended initialization and reset flow for the ALTLVDS_TX and ALTLVDS_RX IP cores.
Initializing ALTLVDS_TX and ALTLVDS_RX
With the ALTLVDS_TX and ALTLVDS_RX IP cores, the PLL is locked to the reference clock prior to
implementing the SERDES blocks for data transfer. The PLL starts to lock to the reference clock during
device initialization. The PLL is operational when the PLL achieves lock during user mode. If the clock
reference is not stable during device initialization, the PLL output clock phase shifts becomes corrupted.
When the PLL output clock phase shifts are not set correctly, the data transfer between the high-speed
LVDS domain and the low-speed parallel domain might not be successful, which leads to data corruption.
Assert the
pll_areset
port for at least 10 ns, and then deassert the
pll_areset
port and wait until the
PLL lock becomes stable. After the PLL lock port asserts and is stable, the SERDES blocks are ready for
operation.
When using DPA, further steps are required for initialization and reset recovery. The DPA circuit samples
the incoming data and finds the optimal phase tap from the PLL to capture the data on a receiver channel-
UG-MF9504
2014.12.15
Effects of DPA PLL Calibration 51
LVDS SERDES Transmitter/Receiver IP Cores User Guide Altera Corporation
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