Altera LVDS SERDES Transmitter / Receiver - Manual (Page 69)

Date Version Changes
June 2013 2013.06.10 • Removed Use clock pin parameter. This parameter is no longer
available for the megafunction beginning from ACDS 13.0.
• Updated Table 1 to include Arria V, Arria V GZ, and Stratix V
device family support. Also added a note to clarify that Altera
recommends implementing the Bus LVDS (BLVDS) I/O with user
logic, instead of the ALTLVDS_TX and ALTLVDS_RX megafunc‐
tions.
• Updated Table 5 and Table 6 to remove Stratix V device family
support and to clarify that In Cyclone series, except Cyclone V, the
SERDES is always implemented in logic cells for the Implement
Deserializer circuitry in logic cells option.
• Updated Table 5 to clarify that the values for the What is the phase
alignment of 'tx_in' with respect to the rising edge of 'tx_
inclock'? (in degrees) option is device dependent.
• Updated Table 5 and Table 6 to remove Stratix V device family
support for the Enable self-reset on lost lock in PLL, Enable PLL
Calibration, and Use 'dpa_pll_recal' input port options.
• Updated Table 6 to add Arria V and Arria V GZ devices support
for the Enable Dynamic Phase Alignment mode, Use 'rx_
divfwdclk' output port and bypass the DPA FIFO, Use 'rx_dpa_
locked' output port, Use a DPA initial phase selection of, and
Align DPA to rising edge of data only options.
• Updated Table 6 to clarify that the values for the What is the phase
alignment of 'rx_in' with respect to the rising edge of 'rx_
inclock'? option is device dependent.
• Updated Table 6 to add the Is this interface constrained to the
left, or right banks? option.
• Updated to add Arria V and Arria V GZ devices support for
common_rx_tx_pll
.
• Updated to remove Stratix V device family support for the
deserialization_factor
,
use_no_phase_shift
,
use_external_
pll
, and
pll_self_reset_on_loss_lock
(Stratix V devices do not
support SERDES using logic cells).
• Updated to add Arria V and Arria V GZ devices support for
deserialization_factor
.
• Updated to add Arria V and Arria V GZ devices support for
inclock_data_alignment
,
outclock_divide_by
,
outclock_
duty_cycle
,
outclock_resource
,
registered_input
, and
use_
external_pll
.
• Updated to add Arria V, Arria V GZ, Cyclone V, and Stratix V
devices.
UG-MF9504
2014.12.15
Document Revision History 69
LVDS SERDES Transmitter/Receiver IP Cores User Guide Altera Corporation
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