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Altera LVDS SERDES Transmitter / Receiver User Manual

Page 31

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Parameter

Type

Description

output_data_rate

Integer

Specifies the data rate out of the PLL. The multiplica‐

tion value for the PLL is

OUTPUT_DATA_RATE/

INCLOCK_PERIOD

.

Only available for Arria GX, Arria II GX, Arria II GZ,

Cyclone, Cyclone II, Cyclone III, Cyclone IV,

HardCopy II, HardCopy III, HardCopy IV, Stratix,

Stratix GX, Stratix II, Stratix II GX, Stratix III, and

Stratix IV devices.

pll_bandwidth_type

String

Specifies the loop filter bandwidth control setting on

the PLL. The values are

LOW

,

MEDIUM

, and

HIGH

.

This parameter is only available for the Stratix II

device.

pll_self_reset_on_loss_lock

String

The values are

ON

and

OFF

. If omitted, the default

value is

OFF

. When this parameter is enabled, the PLL

is reset when it loses lock.
This parameter is valid for Arria V, Arria V GZ,

Cyclone III, Cyclone IV, Stratix, Stratix II GX, Stratix

III, and Stratix IV devices when the

implement_in_

les

parameter is set is

ON

.

registered_input

String

Indicates whether the

tx_in[]

port is registered. The

values are

ON

,

OFF

,

TX_INCLOCK

, and

TX_CORECLOCK

. If

omitted, the default value is

ON

when using the

tx_

coreclock

port to register the data in logic elements.

The

TX_INCLOCK

and

TX_CORECLOCK

values are

available for Arria GX, Arria II GX, Arria II GZ, Arria

V, Arria V GZ, Cyclone, Cyclone II, Cyclone III,

Cyclone IV, HardCopy II, HardCopy III, HardCopy

IV, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix

III, Stratix IV, and Stratix V devices.
If the

registered_input

parameter is set to

OFF

, you

must pre-register the

tx_in[]

port in the logic

feeding the transmitter.

use_external_pll

String

Specifies whether the ALTLVDS_TX IP core

generates a PLL or connect to a user-specified PLL.
Altera recommends instantiating the external PLL

with the parameter editor.
Only available for Arria GX, Arria II GX, Arria II GZ,

Arria V, Arria V GZ, Cyclone, Cyclone II, Cyclone

III, Cyclone IV, HardCopy II, HardCopy III,

HardCopy IV, Stratix, Stratix GX, Stratix II, Stratix II

GX, Stratix III, Stratix IV, and Stratix V devices.

UG-MF9504

2014.12.15

Command Line Interface Parameters

31

LVDS SERDES Transmitter/Receiver IP Cores User Guide

Altera Corporation

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