Altera LVDS SERDES Transmitter / Receiver User Manual
Page 32

Parameter
Type
Description
use_no_phase_shift
String
When set to
OFF
, a phase shift of 90° is added to the
clock to center the clock in the data. Use this
parameter when the
implement_in_les
parameter
value is set to
ON
for Cyclone II, Stratix II, Stratix III,
and Stratix IV devices. The values are
ON
and
OFF
. If
omitted, default value is
ON
. Altera recommends
setting this parameter to
OFF
unless you have
completed a phase adjustment.
The following table lists the
DESERIALIZATION_FACTOR
and
outclock_divide_by
values.
Table 8: DESERIALIZATION_FACTOR and OUTCLOCK_DIVIDE_BY Values
Devices
DESERIALIZATION_FACTOR
Value
OUTCLOCK_DIVIDE_BY Value
Arria GX, Arria II GX,
Arria II GZ, Arria V, Arria
V GZ, HardCopy II,
HardCopy III, HardCopy
IV, Stratix II, Stratix II GX,
Stratix III, Stratix IV, and
Stratix V
4
2
4
5
5
6
2
6
7
7
8
2
4
8
9
9
10
2
10
Stratix and Stratix GX
4
2
4
7
7
8
2
4
8
10
2
10
32
Command Line Interface Parameters
UG-MF9504
2014.12.15
Altera Corporation
LVDS SERDES Transmitter/Receiver IP Cores User Guide
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)