Achronix Speedster22i SerDes - Manual (Page 94)

Note: Although the PCS modules are disabled, the SerDes will still generate two clocks for
transmit and receive ends (from PMA). Unlike the design with EFIFO enabled
(simple_serdes_design_efifo), these two clocks are not aligned.
The changes for this derivative of the design are presented below.
Modification – 1 (ACE GUI):
Mode – a (Bypassing PCS Modules without Disabling PCS): While generating GUI wrapper for
this derivative, we need to disable the followings:
1. 8b/10b encoder module in RX PCS Settings window,
2. Symbol alignment module in RX PCS Symbol Alignment window, and
3. 8b/10b decoder in TX PCS Settings window.
Details on these windows have been presented while explaining the design flow for the
baseline design.
Mode – b (Disabling PCS that essentially disables all PCS blocks): In this mode, the PCS block is
completely disabled.
This can be done by disabling the PCS from ACE GUI as shown in
Figure 41 Disabling PCS from ACE GUI. Please note that for the baseline design
simple_serdes_design, the box was left unchecked (Figure 31: PCS Settings Window – First
page).
Modification – 2 (Design RTL): With respect to the sample design (simple_serdes_design), this
variant with PCS bypassed will require only one change in top-level design due to the fact
that comma character is not longer required. Corresponding changes in the module
data_generation is presented below:
module data_generation (
input clk,
input rst_n,
input data_gen_en,
output [39:0] data_out
);
always @ (posedge clk)
begin
if (rst_n == 1'b0)
data_out <= 40’b0;
// *** Comment out the comma-character generation
// *** data_out <= {10'h000,10'h1BC,10'h000,10'h1BC};
else if (data_gen_en == 1’b1)
// when data-generation enabled, i.e. TX_ready from SerDes is up
// *** Logic for data-generation goes here, such as PRBS-7 ***
else
data_out <= 40’b0;
// *** Comment out the comma-character generation
// ***data_out <= {10'h000,10'h1BC,10'h000,10'h1BC};
end
endmodule
94 UG028, July 1, 2014