Achronix Speedster22i SerDes - Manual (Page 28)

EFIFO Standards and Skip Characters
PCIe Gen3: To support PCIe Gen3, 4-bytes of skip are added at byte positions 4-7 from the
sync header associated with the skip ordered set. Skip removal happens from bytes 0-3 from
the sync header associated with the skip ordered set. Due to this particular rule of removal,
sync header and receive start block indications are delayed by 4-bytes.
PCIe Gen1/Gen2: For PCIe Gen1/Gen2, the skip ordered set is two 10-bit words – the elastic
buffer adds or deletes only the second word.
Fiber Channel: To support Fiber channel, 4-bytes of skip are added and deleted. The PCS
operates in 16-bit data-path mode at the fabric interface and 20-bit encoding internally.
XAUI: To support XAUI, the skip ordered set is one 10-bit word, which is added or deleted
by the elastic buffer.
GigE: For GigE, the skip ordered set is two 10-bit words – control followed by data. The
elastic FIFO adds or removes both of these two 10-bit words.
Other Standards: Besides these specific standards, the elastic FIFO can handle any generic
protocols in the similar line due to the programmable nature of SKIP and inverted SKIP
ordered set of length 2. The user has flexibility to include an alternate (mostly inverted) word
in the ordered set. Beyond two words skip ordered sets, only 4 words skip ordered sets can
be used, which are specific to fiber channel. The elastic FIFO generates the final data valid
from the PCS, which is used by the fabric to register data.
28 UG028, July 1, 2014