Achronix Speedster22i SerDes User Manual
Page 83
The following factors determine how many clocks enter the Core for each SerDes lane or
bonded group of lanes:
•
Use of Hard IP Controllers: If you are using a hard IP controller, such as Interlaken,
Ethernet, or PCIe, then the number of clock resources entering the Core is
determined by the number of clocks on the hard IP controller. All raw SerDes clocks
connect to the hard IP controllers and do not enter the Core. Using the hard IP
controllers significantly reduces the number clock resources needed in the Core,
compared to using raw SerDes.
•
By default, each raw SerDes lane consumes 2 clock resources in the Core: 1 Tx Data
Clock and 1 Rx Data Clock
•
If you are using a data rate greater than or equal to 6 Gbps, then the Wide Bus
interface must be used. Using Wide Bus causes the number of clocks per raw SerDes
lane to double. Each SerDes clock entering the Core is divided by 2, resulting in a
second clock resource for each original clock.
•
If you enable the EFIFO Elastic Buffer in the PCS, each pair of Rx and Tx clocks
become combined into 1 clock, resulting in ½ the clock resources entering the Core.
•
If you enable channel bonding in the PCS, you can bond a group of SerDes lanes
together, resulting in 1 set of master SerDes clocks per the entire bonded group of
SerDes lanes (as opposed to 1 set of clocks per lane). Channel bonding is limited to a
maximum of 12 lanes per bonded group. This can dramatically reduce the number
of clocks entering the Core. For example, if you have 12 non-bonded raw 10 Gbps
SerDes lanes placed on the North side of the chip on lanes 0-11, it will result in 48
clocks coming into the Core (2 per lane x 2 for Wide Bus). That is too many clocks.
Now, if you bond the 12 raw serdes lanes together with channel bonding, you will
only need 4 clocks (for the master lane) entering the Core, resulting in 1/12
th
the
clock resources being consumed. This now easily fits within the 16 clock limit per
Core clock region.
Tips to reduce clock resources:
•
Use hard IP controllers
•
Use channel bonding
•
Use the EFIFO in the PCS
•
Use a data rate of less than 6 Gbps (to eliminate Wide Bus)
The following placement limitations determine where you can place a group of bonded or
non-bonded SerDes lanes:
•
A single raw SerDes lane may be placed on any SerDes site in the device
UG028, July 1, 2014
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