Achronix Speedster22i SerDes - Manual (Page 49)

Design Flow: Creating a SerDes Design
In this chapter, step-by-step instructions for creating a SerDes design are presented:
1. Generation of SerDes wrapper using ACE GUI
2. Design of top-level RTL to instantiate the SerDes wrapper created in step 1.
3. Definition of placement and timing for the SerDes.
4. Design guidelines
This chapter starts with a simple design and presents step-by-step instructions for creating
this design. Later section presents the additional/reduced steps required to prepare the
designs with special features.
The Achronix SerDes reference design Speedster22i_SerDes_1lane_10gbps_PCS_bypass_
RD002 is a variant of the designs presented in this chapter and contains the code base used
for using Achronix SerDes IP.
The first simple design presented in this chapter is named as simple_serdes_design. This is a
single-lane SerDes design with the properties listed below.
Design name : simple_serdes_design
Objective : Send data from fabric to SerDes and read-back data using internal loopback.
Data rate : 10.3125 Gbps
Standard : Generic
Number of lanes : 1
Placement : South lane# 8
Ref. clock : 156.25 Mhz
Data width : 40
PCS blocks : Enabled
8b/10b encoder
8b/10b decoder
Symbol alignment: Automatic mode
Note: clock compensation (EFIFO) not used.
The directory structure is not a hard requirement and the user may change it. The directory
structure for the baseline sample design is shown below; the reference design
Speedster22i_SerDes_1lane_10gbps_PCS_bypass_RD002 uses a similar directory structure.
simple_serdes_design (root for this design)
|- src
|----- ace (will contain the project file for generation of wrapper as well as the ace-
generated wrapper, placement and timing constraint files)
|----- constraints (will contain the user-defined placement and timing constraint files)
|----- tb (will contain the user-defined testbench and other related files)
|----- rtl (will contain the user-defined top-level rtl for the design)
Generating SerDes Wrapper using ACE GUI
This section will focus on creating SerDes wrapper using ACE GUI. The generated files will
be stored in simple_serdes_design/ace folder. ACE will generate the RTL for SerDes wrapper
as well as placement and timing constraint files. The SerDes wrapper module is instantiated
in top-level module; the ace-generated placement and timing constraint files are used to
prepare design-specific constraint files.
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