Achronix Speedster22i SerDes - Manual (Page 23)

Equation 1:
𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 = (𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑃𝑟𝑜𝑔𝑟𝑎𝑚𝑚𝑒𝑑 ∗ 𝑠𝑐𝑎𝑙𝑖𝑛𝑔)
+ ℎ𝑎𝑙𝑓 𝑡ℎ𝑒 𝑤𝑖𝑑𝑡ℎ 𝑜𝑓 𝑑𝑎𝑡𝑎 − 𝑝𝑎𝑡ℎ
The assert signal from Transition Density Checker can be taken to fabric.
Note: Any bit transition would cause the counter to clear and the count to restart.
Polarity Bit Reversal (PBR)
The polarity bit reversal block is used to invert data, swap byte ordering, and reverse bit-
ordering. There are two such PCS blocks on the receive path, corresponding to the two
polarity bit reversal blocks on the transmit path.
When the polarity bit reversal on transmit path is performed before protocol encapsulation
(PBR #0 on “Figure 6: PCS Transmitter Block Overview”), the PBR block after protocol
encapsulation is used on receive path (PBR #0 on “Figure 13: - PCS Receive Block
Overview”). In contrast, if PBR operation is performed on encoded data on the transmit path
(PBR #1 on “Figure 6: PCS Transmitter Block Overview”), the PBR block before symbol
alignment/decoder block is used on the receive path (PBR #1 on “Figure 13: - PCS Receive
Block Overview”). As noted earlier, both of these blocks can be disabled, both on the transmit
and the receive paths.
Symbol Alignment
Symbol alignment uses alignment and sequence characters for identifying the correct symbol
boundary in the received data-stream. Attributes for alignment and sequence detect symbols
are specified to be 10-bit wide. But when received data-path is in 8-bit (or 16-bit) wide mode,
only the lower 8-bits of attribute will be considered.
The symbol alignment block can be configured to support a variety of standards. Some of
these standards are listed below:
• PCIe
• XAUI
• GigE
• Infiniband
• Serial Rapid IO
• SPI-5 (lock to training pattern)
• CPRI
• OBSAI
• Fiber Channel
Symbol alignment can be programmed to function in the following modes:
• Manual Mode
• Bit slip Mode
• Automatic Mode
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