Achronix Speedster22i SerDes - Manual (Page 70)

Generation of Wrapper Files:
The user can now generate wrapper files (src/ace folder) by clicking the Generate button.
Note: The user can generate the wrapper files without going through all the pages. In other
words, the user can use Generate button from any page to generate the wrapper files. If the
user does not set values for one or more multiple pages, ACE will use the default values for
the corresponding configurations.
When the user clicks the Generate button, a pop-up window, as shown in “Figure 35:
Generating the Wrapper Files” will be displayed.
Figure 35: Generating the Wrapper Files
The wrapper file locations and the names are based on the directory structure that have been
used to create this design.
The option Register Dump File is disabled here. If the option is chosen with the file name, the
corresponding file will provide the values of the PMA/PCS registers, based on the choices
made by the user while generating the wrapper.
The option VHDL Model can be used to generate a wrapper in VHDL. The resulting VHDL
file is essentially a wrapper that instantiates the Verilog model for the SerDes wrapper.
70 UG028, July 1, 2014