Test bench setup for simulation – Achronix Speedster22i SerDes User Manual

Page 79

create_generated_clock iSERDES.x_ch0.iffdmux.GEN_CLKDIV.TX.iTXclkdiv/clk_out –source

iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_TX_data_clk -divide_by 2

create_generated_clock iSERDES.x_ch0.iffdmux.GEN_CLKDIV.RX.RX.iRXclkdiv/clk_out -

source iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_RX_data_clk -divide_by 2

# Complete: ACE - generated constraints

# Clock-grouping : For Both ACE-generated and design-specific clocks

# The user may refer to the ACE documentation for further details on clock-grouping (???)

# Grouping all clocks: helps decision making during the place-and-route

set_clock_groups -asynchronous -group

{iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_RX_data_clk}\

-group {iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_TX_data_clk} \

-group {iSERDES.x_ch0.iffdmux.GEN_CLKDIV.TX.iTXclkdiv/clk_out} \

-group {iSERDES.x_ch0.iffdmux.GEN_CLKDIV.TX.iRXclkdiv/clk_out} \

-group {tck core_tck}

-group {i_sclk}

Test bench Setup for Simulation

Based on the primary inputs and primary outputs listed in “Table 20: Signals passed between

below:

module tb_fab_pcs_pma_no_ebuf_1ln_10p3125gbps_156p25mhz();

reg ch0_ref_clk_p;

reg ch0_reset_signal;

reg ch0_RX_output;

initial

begin

ch0_ref_clk_p = 1'b0 ;

ch0_reset_signal = 1'b0 ;

#4000;

ch0_reset_signal = 1'b1 ;

end

// Generating 156.25 MHz reference clock

always #3200 ch0_ref_clk_p = ~ch0_ref_clk_p;

fab_pcs_pma_no_ebuf_1ln_10p3125gbps_156p25mhz DUT(

// Okay to tied to 1'b1

.ln0_RX_m (1'b1),

.ln0_RX_p (1'b1),

// 156.25 MHz differential reference clocks

.ln0_refclk_m (~ch0_ref_clk_p),

.ln0_refclk_p (ch0_ref_clk_p),

// Same reset input for hard-reset, RX-reset & TX-reset

.ln0_rst_n_RX (ch0_rst_hard_n),

.ln0_rst_n_TX (ch0_rst_hard_n),

.ln0_rst_hard (ch0_rst_hard_n),

.ln0_RX_data (ch0_RX_output)

);

Endmodule

UG028, July 1, 2014