Achronix Speedster22i SerDes - Manual (Page 100)

The Ports of ACX_SERDES_SBUS_IF Module:
The signals (ports) shown in “Figure 43 Changing Value of Register 17A to bypass PCS
block” and “The Ports of ACX_SERDES_SBUS_IF Module:” are detailed now.
General signals:
Port sbus_clk: There should be one ACX_SERDES_SBUS_IF instance per SerDes lane. For
each lane, a clock signal is required to drive both the SerDes (input ports ch0_i_sbus_clk etc.)
and ACX_SERDES_SBUS_IF (input port sbus_clk). The sbus_clk may be shared with multiple
Serdes lanes. The sbus_clk is normally generated by a PLL, and, for practical reasons, should
be 50MHz or less. You cannot use the RX or TX clock for this.
Port rstn: The active-low rstn signal must be asserted briefly at start-up to initialize the
interface. Deassertion should be synchronous to sbus_clk.
Port sbus_sw_rst: The synchronous sbus_sw_rst signal is optional. It can be used with a
timeout counter: when a timeout occurs, sbus_sw_rst is asserted (active-high) to reset the
internal state machine to its start state. However, unless there is some internal failure, no
timeout should occur. If this mechanism is not needed, the sbus_sw_rst pin can be tied to
GND. (If you want to add a timeout, allow at least 64 cycles per read or write.)
SerDes signals:
SerDes interface ports – from_sbus and to_sbus: As shown in “Figure 45 Connections for
ACX_SERDES_LOOPBACK_CTRL”, the from_sbus inputs must be driven by the matching
SerDes outputs, and the to_sbus output must drive the matching SerDes inputs. The user will
also find an example of this constraint when we will present the example of setting loopback
mode using SBUS interface.
Parallel Interface signals:
Ports i_reg_rw_req and o_reg_rdwr_valid: A register read or write is triggered by a rising
edge on i_reg_rw_req, and completion is signaled by o_reg_rdwr_valid.
Port i_reg_write and i_reg_wr_data: The i_reg_write input indicates whether the requested
action is a read or a write. For a write, the 8-bit register value is passed via i_reg_wr_data. All
inputs (data and address) are registered internally by the interface.
Ports i_reg_pma and i_reg_address: The SerDes has two sets of registers, PCS registers and
PMA registers. Both have their own 16-bit address space (not all addresses are used). If
i_reg_pma is high, i_reg_address is a PMA address; otherwise it is a PCS address.
Port o_reg_rdwr_valid and o_reg_rd_data: Completion of a read or write is signaled by
o_reg_rdwr_valid high. This signal is high for only one cycle. For a read, the register value is
available on o_reg_rd_data, but only for the cycle where o_reg_rdwr_valid is high. You can
latch this signal as:
if (!i_reg_write && o_reg_rdwr_valid)
my_reg <= o_reg_rd_data;
Note: A write operation writes all 8 bits of the register. To modify only selected bits, you
need to perform a read-modify-write: read the register value, modify the value locally, then
write the result back.
100 UG028, July 1, 2014