Achronix Speedster22i SerDes - Manual (Page 102)

SerDes signals
Sbus_clk and ready signals: The sbus_clk and ready signals must be connected between
SerDes lane and ACX_SERDES_LOOPBACK_CTRL. The sbus_clk must be connected to both
SerDes lane and ACX_SERDES_LOOPBACK_CTRL. The sbus_clk may be shared with
multiple SerDes lanes. The sbus_clk is normally generated by a PLL, and, for practical
reasons, should be 50MHz or less. You cannot use the RX or TX clock for this.
Control signals
Signal done: When ACX_SERDES_LOOPBACK_CTRL has finished configuring the Serdes, it
raises done.
Signal disable_loopback: The disable_loopback input can be used to dynamically disable
loopback mode. Asserting and de-asserting rstn will enable loopback mode again, as will a
reset of the SerDes.
Note: If for some reason you want to re-apply the Serdes hard reset (i_rst_hard_n) after the
design has been running for a while, then you must first disable loopback, using
disable_loopback. When the Serdes comes out of hard reset, the loopback mode will
automatically be re-enabled.
Pass-through signals:
Most designs don't need the pass-through signals.
Loopback Modes
Please refer to Section - Loopback Modes for the valid loopback modes available with
Achronix FPGA.
Example Code
wire loopback_done;
wire [1:0] from_sbus_data, to_sbus_data;
wire from_sbus_ack, to_sbus_req, to_sbus_sw_rst;
wire pma_synthready, pma_TXready, pma_RXready;
ACX_SERDES_LOOPBACK_CTRL #(
.LOOPBACK_MODE(`LPBK_TX_RX_PMA_INTERNAL),
.ENABLE_PASS_THROUGH(0)
) loopback_ch0 (
.sbus_clk(sbus_clk),
.rstn(1'b1),
.disable_loopback(1'b0),
.done(loopback_done),
// serdes connections
.from_sbus_data(from_sbus_data),
.from_sbus_ack(from_sbus_ack),
.to_sbus_data(to_sbus_data),
.to_sbus_req(to_sbus_req),
.to_sbus_sw_rst(to_sbus_sw_rst),
.i_pma_synthready(pma_synthready),
.i_pma_TXready(pma_TXready),
102 UG028, July 1, 2014