Achronix Speedster22i SerDes - Manual (Page 8)

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Programmable spread spectrum generation
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Support for 16-bit fractional multiplication factors
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Programmable spread spectrum clocking
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Support for fast lock mode for EPON/GPON
• On-chip scope in the receiver for measuring eye width, eye height and BER for the
incoming signal
• On-chip calibrated 100 ohm termination
• Transparent calibration engine to compensate for PVT variation
Clocking
• Support for external reference clock from 50 MHz – 300 MHz
• Support for recovered reference clock for loop timing and re-timer type applications
that eliminates the need for a cleanup PLL
Physical Coding Sublayer (PCS)
• Bypassable and Modular PCS architecture
• Support for 8b/10b and 128b/130b encoding
• Symbol alignment
• Clock and phase compensation FIFO
• Lane to lane de-skew
• Polarity inversion
• Bit reversal
• Lane bonding
• Low/Deterministic latency modes for protocols such as CPRI and OBSAI
Debug and Test
• Up to seven different near-end and far-end loopback modes in PMA and PCS
• Built-in self test (BIST)
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PRBS 7, 15, 23, 31 and 40-bit user defined pattern generators and checkers in
the PCS
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PRBS 7, 23, 31 and 40-bit user defined pattern generators and checkers in the
PMA
8 UG028, July 1, 2014