Achronix Speedster22i SerDes - Manual (Page 7)

Chapter 1 – SerDes Architecture
Overview
Achronix Speedster22i FPGAs provide very high core fabric and I/O performance which
exceeds the system bandwidth requirements of various high end applications. The
Speedster22i device family supports up to 64 full-duplex SerDes lanes, each supporting up to
11.3 Gbps data rate.
The Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sub-blocks
together comprise a single SerDes block. The SerDes PCS has explicit support for PCIe,
10GBASE-R, 1G Ethernet and XAUI. It also has some support for various other interconnect
protocols through PCS such as Interlaken, SPI4.2, Infiniband, Fiber-Channel, SAS/SATA,
SONET, OC, OBSAI and CPRI. The SerDes can be connected either to the embedded Hard-
IPs (PCIe, Interlaken, and 10/40/100G MAC) or to the FPGA Fabric for soft implementation of
any other protocol supported.
Physical Media Attachment (PMA)
• Data rates supported
o
1.0625 – 11.3 Gbps
o
531.25 – 1062.5 Mbps using 2X over-sampling
o
265.625 – 531.25 Mbps using 4X over-sampling
• Independent lane architecture with dedicated synthesizer for each lane with no off-
chip components required
• Low power architecture (<100mW at 10Gbps)
• Support both AC and DC coupling
• Input driver with Continuous Time Linear Equalizer (CTLE) and Decision Feedback
Equalizer (DFE)
o
Input voltage: 50 – 2000 mVp-p differential
o
Auto-calibrating CTLE and DFE
o
CTLE with up to 20dB gain tuned for key data rates
o
Pulse-shaped 5-tap DFE
• Output driver with 4-tap Finite Input Response (FIR) filter with Feed Forward
Equalizer (FFE)
o
Output voltage: 400 – 1500 mVp-p differential
o
Slew rate: 31 – 170 ps
• Highly digital PLL architecture for the Synthesizer and CDR
o
Accuracy & low jitter of an analog PLL
o
Tuning range of a digital PLL
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