Serdes architecture overview, Figure 2: serdes architecture – Achronix Speedster22i SerDes User Manual
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SerDes Architecture Overview
The SerDes has an independent lane architecture. Each lane has a Physical Media Attachment
(PMA), Synthesizer (Transmit PLL), Clock and Data Recovery (CDR) and Physical Coding
Sublayer (PCS). The Receiver PMA and Transmitter PMA block diagrams are shown in
“Figure 2: SerDes Architecture” below.
Figure 2: SerDes Architecture
The SerDes primarily consists of the following blocks:
•
PMA
•
PCS
•
PCS interface to FPGA fabric
•
Clocking
•
Debug and Test
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UG028, July 1, 2014