Achronix Speedster22i SerDes - Manual (Page 77)

Note: When 10’h1BC is transmitted from the fabric, the output of the 8b/10b decoder on the
PCS receiver path will be 10’h283 (alternate: 10’h17C).
The code for data_generation module that includes comma-characters is shown below
module data_generation (
input clk,
input rst_n,
input data_gen_en,
output [39:0] data_out
);
always @ (posedge clk)
begin
if (rst_n == 1'b0)
// comma-characters when SerDes in reset-state (active-low reset)
data_out <= {10'h000,10'h1BC,10'h000,10'h1BC};
else if (data_gen_en == 1’b1)
// when data-generation enabled, i.e. TX_ready from SerDes is up
// *** Logic for data-generation goes here, such as PRBS-7 ***
// *** Should also contain comma characters ***
else
// comma-characters when data generation is ‘not’ enabled
ln0_TXdata <= {10'h000,10'h1BC,10'h000,10'h1BC};
end
endmodule
Using the clocks from SerDes: This sample design has the EFIFO disabled. Hence, two clocks
are provided by the SerDes for the fabric: TX-clock and RX-clock. These two clocks may not
be aligned with each other. To avoid the false paths, the user needs to use the TX-clk on the
transmitter datapath (such as data generation for SerDes) and the RX-clk on the receive data
path (such as checking the received data from SerDes for correctness).
Placement of SerDes
The placement file used for the simple_serdes_design is: src/constraints/ace_placement.pdc.
This file contains the placement information for the followings:
• Placement information for the SerDes instance
• Clock/reset inputs to the SerDes
• Debug signals that the user may want to bring outside the FPGA.
The placement of SerDes depends on the lane that the user wants to use. While generating
the wrapper from ACE GUI, lane# 8 has been chosen for placement (“Figure 23: New IP
Configuration Window- Overview Page”). The consequent placement in
simple_serdes_design_wrapper.pdc file will be:s
set_placement -batch -fixed { i:x_ch0.u_serdes_wrap.u_serdes } {
s:te_serdes_12lane_top_i1.u_serdes_lane_top_wrap_i0.u_serdes_lane_top }
Since, the SerDes instance as iSerDes in the top-level module, the placement needs to be
modified as:
set_placement -batch -fixed { i:iSerDes.x_ch0.u_serdes_wrap.u_serdes } {
s:te_serdes_12lane_top_i1.u_serdes_lane_top_wrap_i0.u_serdes_lane_top }
For information about how to place the clock signals, reset signals (such as rst_hard in the
listing above) and other debug signals (such as ln0_synthready), please refer to the UG001 –
ACE Users Guide. For the Speedster22i HD1000 Development Kit, the following three show
UG028, July 1, 2014 77