Achronix Speedster22i SerDes - Manual (Page 80)

Design Guidelines
This section will first present the coding practice that the user is recommended to use.
Reset Sequence
The following sequence is presented as a guidance to define the reset sequence to be used
with a typical SerDes application.
1. Deassert hard-reset (ch0_i_rst_hard_n in “Table 20: Signals passed between the SerDes
Instance and the Top-Level module”)
2. Wait for 1200us; registers within SerDes can be programmed during this time. Deassert
the ch0_i_iddq_n resets in “Table 20: Signals passed between the SerDes Instance and the
Top-Level module”.
3. Deassert the reset ch0_i_TX_rst_n on PCS-TX data-path
4. Wait for 850us.
5. Deassert the reset ch0_i_RX_rst_n on PCS-RX data-path
Notes:
1. The reference clocks on all instantiated serdes lanes MUST be running during
programming the bitstream on the HD1000 device to properly configure the SerDes.
2. Dynamic functions like Loopback mode, BIST and SSC generation must be disabled
when programming the bitstream. These functions have to be enabled through SBUS after
bitstream programming.
SerDes Placement and Clocking Limitations
Although there are 64 independent raw SerDes lanes available on the device, there are
restrictions on how many lanes can effectively be used in a given design, depending on
placement and configuration of SerDes clocks entering the Core. All 64 SerDes lanes may be
used in a design, as long as the clock and placement criteria are met. Below is a list of rules
you can use to determine if your design’s SerDes configuration will be supported on the
device.
Note: There are workarounds for some corner cases that violate the SerDes placement and
clocking limitations. Please contact support to discuss if your corner case design has a
workaround or not
Clock resource limitations in the Core:
• The Core is divided into clock regions as seen in the figure below. The clock regions
are split by the clock trunk (vertically) and the clock branches (horizontally), forming
a set of clock regions on the West and another set on the East.
• Each clock region is capable of handling 16 clock resources
• All clocks from SerDes lanes 0 to 14 on the North Side of the Chip enter the far
NorthWest clock region.
• All clocks from SerDes lanes 20 to 31 on the North Side of the Chip enter the far
NorthEast clock region.
• All clocks from SerDes lanes 15 to 19 on the North Side of the Chip enter BOTH the
far NorthWest and far NorthEast clock regions. Avoid using these lanes if possible.
80 UG028, July 1, 2014