Achronix Speedster22i SerDes - Manual (Page 34)

XAUI
The PCS supports XAUI compliant with section 48 of IEEE 802.3. The Protocol block
implements the Transmit and Receive state machines as per Figures 48-6 and 48-9 of IEEE
802.3. For synchronization, de-skew and clock compensation operations, symbol alignment,
de-skew and elastic buffers in PCS are used. 8b/10b encoders and decoders are used for
handling 10-bit code groups.
When communicating with the XGMII (fabric side), the PCS uses in each direction 32 data
signals and 4 control signals. When communicating with the PMA, the PCS uses a 40-bit
code-group in the transmit direction and in the receive direction. Each set of 40-bit data
signals conveys four lanes of 10-bit code-groups. The 40-bit code-group signals are organized
into four lanes: the first PCS code-group is aligned to lane 0, the second to lane 1, the third to
lane 2, and the fourth to lane 3. Code-group alignment, lane-to-lane de-skew, and provision
for clock rate compensation are made possible by embedding special non-data code-groups
in the idle stream.
The PCS Transmit process continuously generates code-groups based upon the TXd [31:0]
and TXc [3:0] signals on the XGMII, sending them to the PMA service interface.
The PCS Synchronization process indicates whether the PMA is functioning dependably,
which can be determined without exhaustive error-rate analysis. The PCS Synchronization
process continuously accepts unaligned and unsynchronized code-groups from the PMA,
obtains 10-bit code-group synchronization, and conveys synchronized 10-bit code-groups to
the PCS de-skew process as per Figure 48-7 in IEEE 802.3.
The PCS de-skew process continuously accepts synchronized code-groups, aligns the code-
groups to remove skew between the lanes introduced by the link, and conveys aligned and
synchronized code-groups to the PCS Receive process. At the end of the de-skew process, the
PCS will have successfully de-skewed and aligned code-groups on all PCS lanes. The de-
skew process always looks for non-aligned code-groups across 4-lanes and initiates de-skew
operations as per Figure 48-6 in IEEE 802.3.
Clock rate compensation is required when the received clock from the PMA and the clock on
which data is sent to fabric are different in terms of jitter. The PCS compensates by inserting
or deleting SKIP (||R||) characters in the encoded idle stream. Insertion and deletion is only
done after SKIP (||R||) is detected – not arbitrarily on any positions.
The Receive process operates in two modes as per Figure 48-9 in IEEE 802.3: date and idle
mode. In data mode, valid code-groups received are mapped to corresponding XGMII data
or control characters regardless of whether the control characters are valid XGMII control
characters. Invalid or error code-groups are mapped directly to XGMII Error control
characters. In idle mode, an idle code-group is translated to XGMII Idle control characters.
All code-groups are mapped on a lane by lane basis.
PIPE Interface
The PCS supports the PIPE interface compliant to the Intel PIPE 3.0 specification. It supports
a 10/20-bit data path for gen1/gen2 and 16-bit for gen3. Similarly, it supports 2.5G, 5.0G and
8.0G throughput on the PMA. For gen1/gen2, 8b/10b endec and gen3 128b/130b endec are
used. This interface allows the embedded PCIe MAC to configure the PMA and decide upon
the next course of action based on the status sent out by the PMA. Besides the functions
described in the PIPE interface specifications, it facilitates the MAC in setting up the receive
equalizer in the PMA. When the PCS is supporting PCIe/PIPE, lane de-skew is done by the
MAC and clock compensation is done by the elastic buffer in the PCS.
The PCS also supports a 128b/130b encoder, specifically targeted for PCIe gen3 (based on
draft 0.5 of the PCIe 3.0 specification). The interface is compliant to the PIPE 3.0 specification.
34 UG028, July 1, 2014