Achronix Speedster22i SerDes - Manual (Page 72)

Integration of SerDes Wrapper in a Design
This section details how to use the files generated by ACE GUI into a user-design. For ready-
reference, the design properties from “Design Flow: Creating a SerDes Design” are presented
again:
Design name : simple_serdes_design
Objective : Send data from fabric to SerDes and read-back data using internal loopback.
Data rate : 10.3125 Gbps
Standard : Generic
Number of lanes : 1
Placement : South lane# 8
Ref. clock : 156.25 Mhz
Data width : 40
PCS blocks used :
8b/10b encoder
8b/10b decoder
Symbol alignment: Automatic mode
Note: clock compensation (EFIFO) not used.
The simple_serdes_design will contain the following files:
• simple_serdes_design_top.v: Top-level RTL that will instantiate the SerDes wrapper
generated by ACE. As per the directory structure as shown above, this file will be
under src/rtl sub-directory.
• simple_user_design_wrapper.v: The SerDes wrapper RTL that has been generated by
ACE. (Under src/ace directory.)
• data_generation.v: This will include the code used to generate data for transmission,
including comma characters. (Under src/rtl sub-directory.)
• simple_user_design.pdc: ACE Placement file. (Under src/constraints sub-directory.)
• simple_user_design.sdc: ACE constraint file for timing. This will contain the timing
constraints from the ACE-generated simple_serdes_design_wrapper.sdc file as well
as constraints related to the additional clocks used in simple_user_design_top.v.
(Under src/constraints sub-directory.)
• tb_user_guide.v: This is the testbench used for design; we will use this for simulation
purposes. (Under src/tb sub-directory.)
The Achronix SerDes reference design Speedster22i_SerDes_1lane_10gbps_PCS_bypass_
RD002 can be referred for further understanding on how the ACE GUI generated files can be
used in a design.
Design and Wrapper Files
simple_serdes_design_top.v: This is the top-level module for the current design. This module
will instantiate the SerDes wrapper (from simple_design_wrapper.v file) and will use the
SerDes ports to: (a) send data to SerDes and (b) read-back data from SerDes. Some SerDes
ports are also brought to the FPGA I/O pads as reset and debug signals.
The ports that are available from the SerDes wrapper are displayed in “Figure 25: IP Diagran
Window”. To instantiate the wrapper module simple_serdes_design_wrapper, the following
construct is used:
simple_serdes_design_wrapper iSerDes
where, iSerDes is the name of the instance. The instance name iSerDes is used in other files as
well, such as the ace_placement.pdc and the ace_constraint.sdc files. If the instance name
72 UG028, July 1, 2014