Achronix Speedster22i SerDes - Manual (Page 33)

PCS Interface
The PCS interface provides the general interface between the PCS and the core fabric. The
PCS supports the following interfaces:
• Gigabit Ethernet Interface
• XAUI
• PIPE Interface
• 10G Ethernet Interface
Gigabit Ethernet Interface
The PCS in Achronix SerDes supports 10G Ethernet, compliant with section 36, 37 of IEEE
802.3. Functionalities implemented are PCS transmit, carrier sense, synchronization, receive,
and auto-negotiation.
The PCS transmit process is facilitated at both the GMII and PMA interfaces to the PCS. At
the GMII interface (fabric side), the PCS uses 8-bit synchronous data-path with packet de-
limiting, done by separate transmit control (TX_en, TX_err) and receive control signals
(RX_dv, RX_err). At the PMA interface, the PCS uses 10-bit data path, which uses 10-bit code
groups. Besides generating 10-bit code groups continuously based on GMII signals (TXd[7:0],
TX_dv, TX_err), transmit process also generates GMII signal col if reception is concurrent
with transmit. The transmit process also monitors auto-negotiation to determine whether it
needs to send data or reconfigure the link. As part of transmit process, the state machines
shown in Figures 36-15 and 36-16 of IEEE 802.3 are implemented. To enable carrier sense the
PCS generates an internal flag.
The PCS Synchronization process determines whether the PMA is functioning reliably. The
PCS Synchronization process continuously accepts code-groups and conveys received code-
groups to the PCS Receive process. For synchronization, a symbol alignment module is used.
For synchronization, the state machines shown in Figures 36-9 of IEEE 802.3 are
implemented.
The PCS Receive process continuously accepts code-groups. The PCS Receive process
monitors these code-groups and generates RXD <7:0>, RX_DV, and RX_ER on the GMII, and
the internal flag used by the Carrier Sense and Transmit processes. For synchronization, the
state machines shown in Figures 36-7 of IEEE 802.3 are implemented.
The PCS Auto-Negotiation process sets the xmit flag to inform the PCS Transmit process to
either transmit idles interspersed with packets as requested by the GMII or to reconfigure the
link. The PCS auto-negotiation process is specified in the state machine shown in Figure 37-6
of IEEE 802.3. As part of auto-negotiation, the PCS will advertise only as a 1G link full-duplex
partner. The following management registers are currently implemented:
a. Control register (Register 0)
b. Status register (Register 1)
c. AN advertisement register (Register 4)
d. AN link partner ability base page register (Register 5)
These management registers are accessible through SBUS i/f (P1). A MDIO-to-SBUS bridge
can be implemented in the fabric. The reset duration of these controllers is programmable
via register, and the max duration is defined as 0.5sec as per IEEE 802.3.
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