Cirrus Logic AN269 - Manual (Page 55)

AN269
AN269REV1 55
The output mode for this display (taken from table “Output Pixel Transfer Modes“ in the Raster section of the EP93xx
User’s Guide) is “single pixel per clock up to 24 bits wide“ which yields the connections shown in
Table 16 (level
buffering may be required to meet the electrical characteristics).
EP93xx Pin
Name
Corresponding Entry in Table “Output
Pixel Transfer Modes” in the EP93xx
User’s Guide Raster Chapter
LB064V02-B1 Pin Name
(Level shifting may be
required)
LB064V02-B1 Pin
Number
SPCLK X DCLK 5
BLANK X DE 6
VCSYNC X VSYNC 7
HSYNC X HSYNC 8
P[12] R[2] R0 10
P[13] R[3] R1 11
P[14] R[4] R2 12
P[15] R[5] R3 13
P[16] R[6] R4 14
P[17] R[7] R5 15
P[6] G[2] G0 17
P[7] G[3] G1 18
P[8] G[4] G2 19
P[9] G[5] G3 20
P[10] G[6] G4 21
P[11] G[7] G5 22
P[0] B[2] B0 24
P[1] B[3] B1 25
P[2] B[4] B2 26
P[3] B[5] B3 27
P[4] B[6] B4 28
P[5] B[7] B5 29
Table 16. Connections to a LG/Philips LB064V02-B1