An269 – Cirrus Logic AN269 User Manual
Page 39
AN269
AN269REV1
39
Since the remaining region widths are determined by their respective timing parameters, here are some
equations to determine the number of VIDCLK periods required for the display:
LoadHighVidClks = (tVCLHSYNC / VidClkPeriod) + 1
FrameHoldVidClks = [(tVCHHSYNC - tVCLHSYNC) / VidClkPeriod] + 1
LoadCPVidClks = (tHSYNCSPCLK / VidClkPeriod) + 1
CPLoadVidClks = [(tSPCLKHSYNC - tVCLHSYNC) / VidClkPeriod] + 1
Note that 1 is added to the result to round up. Once we have these quantities, the number of remaining
VIDCLKs per line (those not needed by any region) is found by subtracting all of the above quantities from
the number of available VIDCLKs per horizontal line:
AvailableVidClks = NumVideoClocks - ActiveVidClks - LoadHighVidClks - FrameHoldVidClks -
LoadCPVidClks - CPLoadVidClks
If this quantity is negative, there are not enough VIDCLKs per line, and therefore the VIDCLK frequency
must be increased. To do this, go back to
and increase the number of VIDCLKs
for any region that may require more, then recalculate a higher VIDCLK frequency. As mentioned earlier,
this will change the VIDCLK frequency, and therefore the AvailableVidClks. This process may need to be
repeated several times until a suitable VIDCLK frequency is found.
If the AvailableVidClks is 1 or more, then these clocks can be distributed among the various regions (pad-
ding each region) until all remaining VidClks have been assigned. As each clock is distributed, update the
value of ActiveVidClks, LoadHighVidClks, FrameHoldVidClks, LoadCPVidClks, and CPLoadVidClks.
Now that each region is assigned a certain number of VIDCLK periods, determining the register values
for the EP93xx Raster Engine is straightforward (delay offsets included are to compensate for internal de-
lays in the raster engine):
HClksTotal = NumVideoClocks - 1
HSyncStrt = HClksTotal - FrameHoldVidClks
HSyncStop = HClksTotal - FrameHoldVidClks - LoadHighVidClks
HActiveStrt = ActiveVidClks + CPLoadVidClks -1
HActiveStop = CPLoadVidClks - 1
HClkStrt = ActiveVidClks + CPLoadVidClks - 6
HClkStop = CPLoadVidClks - 6
Note that the blank output is not used, so 0 can be assigned to the horizontal blank timing registers:
HBlankStart = 0
HBlankStop = 0