An269 – Cirrus Logic AN269 User Manual
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AN269REV1
AN269
Since the remaining region widths are determined by their respective timing parameters, here are some
equations to determine the number of VIDCLK periods required for the display:
LoadHighVidClks = (tHSYNCH / VidClkPeriod) + 1
FrameHoldVidClks = (tHVCSYNC / VidClkPeriod) + 1
LoadCPVidClks = [(tHSYNCSPCLK - tHVCSYNC) / VidClkPeriod] + 1
CPLoadVidClks = (tSPCLKHSYNC / VidClkPeriod) + 1
Note that 1 is added to the result to round up, and tHSYNCH, tHVCSYNC, etc. are in units of seconds.
Once we have these quantities, the number of remaining VIDCLKs per line (those not needed by any re-
gion) is found by subtracting all of the above quantities from the number of available VIDCLKs per hori-
zontal line:
AvailableVidClks = NumVideoClocks - ActiveVidClks - LoadHighVidClks - FrameHoldVidClks -
LoadCPVidClks - CPLoadVidClks
If this quantity is negative, there are not enough VIDCLKs per line, and therefore the VIDCLK frequency
must be increased. To do this, go back to
and increase the number of VIDCLKs for any sec-
tion that may require more and recalculate the higher VIDCLK frequency (the number of VIDCLKs may
have to be increased until the actual frequency goes up). As mentioned earlier, this will change the VID-
CLK frequency, and therefore the AvailableVidClks. This process may need to be repeated several times
until a suitable VIDCLK frequency is found.
If the AvailableVidClks is 1 or more, than these clocks can be distributed among the various regions (pad-
ding each region) until all remaining VidClks have been assigned. As each clock is distributed, update the
value of ActiveVidClks, LoadHighVidClks, FrameHoldVidClks, LoadCPVidClks, and CPLoadVidClks.
Now that each region is assigned a certain number of VIDCLK periods, determining the register values
for the EP93xx raster engine is straightforward (note offsets where appropriate due to internal delays in
the raster block):
HClksTotal = NumVideoClocks - 1
HSyncStart = LoadHighVidClks + FrameHoldVidClks - 1
HSyncStop = FrameHoldVidClks - 1
HActiveStart = HClksTotal - LoadCPVidClks -1
HActiveStop = HClksTotal - LoadCPVidClks - ActiveVidClks -1
HClksStart = HClksTotal - LoadCPVidClks - 6
HClksStop = HClksTotal - LoadCPVidClks - ActiveVidClks - 6
Note that the blank output is not used, so 0 can be assigned to the horizontal blank timing registers:
HBlankStart = 0
HBlankStop = 0