Cirrus Logic AN269 - Manual (Page 15)

AN269
AN269REV1 15
In “4 Pixels-Per-Shift-Clock mode“, shown in Figure 8 , only 1 bit (the MSB) will be available for the Blue and Green
components of the pixel. The Red component will have the two MSBs available. In this mode, there are 4 pixels
clocked during each SPCLK. As can be seen from the diagram, pixel 0 is output on P[3:0], pixel 1 is output on P[7:4],
pixel 2 is output on P[11:8], and pixel 3 is output on P[15:12]. Note that the diagram does not show bit 6 (the second-
most-significant bit) for the Red component connected to the display, as most displays will only be using 1 bit for
each color in this mode.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pixel
Dat
a Mo
st
Sign
if
ican
t Bit
s
(fr
o
m LUT
a
n
d
Blink
Logic
)
0
0
0
1
1
1
Pixel Data Bus
Pins P[17:0]
Pixels 0, 1, 2 and 3
2
2
2
3
3
3
16
17
0
1
2
3
Figure 8. 4 Pixels Per Shift Clock