Cirrus Logic AN269 - Manual (Page 32)

32 AN269REV1
AN269
Another result of having no “blank” lines is that the active region covers all of the horizontal lines, so the
active region is the entire vertical width:
VActiveStart = VLinesTotal
VActiveStop = VLinesTotal + 1
VActiveStop is set this way to insure that pixel data is not stopped due to vertical position. Also, the
SPCLK should not be stopped due to vertical position:
VClkStart = VLinesTotal
VClkStop = VLinesTotal + 1
The blank signal is not used, but it may be desired to initialize the Vertical Blanking timing registers to a
known value:
VBlankStart = 0
VBlankStop = 0
6.3 Framed Data Style Displays - Type 2
In displays using a framed data style timing interface, the following control signals are commonly used for
data synchronization:
– CP - Data input pixel clock. Usually one rising/falling edge occurs per pixel or set of pixel data. This
is the highest frequency interface signal, and transitions occur many times during each horizontal
line, once for each horizontal pixel.
– FRM - Vertical Synchronization or Frame Signal. Indicates the beginning of a full frame of data. This
signal becomes active one time during a single video frame.
– LOAD - Horizontal Synchronization or Load Signal. Indicates the beginning of the next horizontal
line. This signal becomes active one time during the line, and many times per full video frame.
These signals should be connected to the EP93xx with the signal mapping shown in Table 6 .
Display Pin EP93xx Pin
CP SPCLK
FRM VCSYNC
LOAD HSYNC
Table 6. Frame Type 2 Pin Mapping