2 framed data style displays - type 1, An269 – Cirrus Logic AN269 User Manual
Page 24
24
AN269REV1
AN269
The next two values of interest for a frame are the point at which active data should be clocked out. These
values determine when valid data is presented to the display. As can be seen from the diagram, those
times are identical to the locations at which the active data/blank signal are changing. Using VActiveStart
as the start of active data and VActiveStop as the end of active data:
VActiveStart = VBlankStart
VActiveStop = VBlankStop
The last two values that must be determined are the VClkStart and VClkStop values. These determine
when the SPCLK signal is seen at the output during the full video frame. In situations where clock gating
is not required, these may be set such that SPCLK is always running:
VClkStart = VLinesTotal
VClkStop = VLinesTotal
When clock gating is required, the SPCLK signal is seen at the output when the line counter is in the active
range VClkStart > line counter > VClkStop. If the clock should only be present during valid horizontal lines,
the appropriate values should be assigned as such:
VClkStart = VActiveStart
VClkStop = VActiveStop
The above values must then be shifted properly and assigned to the VLinesTotal, VSyncStrtStop, VAc-
tiveStrtStop, VBlankStrtStop, and VClkStrtStop registers.
For an example calculation for this type of display, see
“Example HSYNC/VSYNC-Style LCD Display -
LB/Philips LB064V02-B1” on page 52
.
6.2
Framed Data Style Displays - Type 1
In displays using a framed data style timing interface, the following control signals are commonly used for
data synchronization:
–
CP - Data Input Pixel Clock. Usually one rising/falling edge occurs per pixel or set of pixel data. This
is the highest frequency interface signal, and transitions occur many times during each horizontal
line, once for each horizontal pixel.
–
FRM - Vertical Synchronization or Frame Signal. Indicates the beginning of a full frame of data. This
signal becomes active one time during a single video frame.
–
LOAD - Horizontal Synchronization or Load Signal. Indicates the beginning of the next horizontal
line. This signal becomes active one time during the line, and many times per full video frame.
These signals should be connected to the EP93xx with the signal mapping shown in