Cirrus Logic AN269 - Manual (Page 22)

22 AN269REV1
AN269
6.1.3 Vertical Alignment Signals
Timings for a single vertical frame can be seen in Figure 12 . The timing of the synchronization signals is
determined by the vertical frame timing registers VLinesTotal, VSyncStrtStop, VActiveStrtStop, VBlank-
StrtStop, and VClkStrtStop.
See “Using the Horizontal and Vertical Counter for Timing-Signal Generation” on page 4 for a description
of the vertical timing registers.
Recall from above that the timing specifications for this type of display interface will list a VCSYNC Width,
Vertical Back Porch Width, Vertical Front Porch Width, Vertical Valid, and Vertical Blank lengths.
The VLinesTotal register will hold the total length of a single frame measured in horizontal lines. It is the
sum of the Vertical Valid (tVACTIVE) region, the Vertical Front Porch Width (tVFRONTPORCH), the VC-
SYNC Width (tVSYNC), and the Vertical Back Porch Width (tVBACKPORCH). The equation for this is
shown here (tVERT is calculated in
Section 6.1.1 ):
VLinesTotal = tVERT – 1
Note that 1 is subtracted for the total as this is a 0-based counter implementation. Also, all measurements
are assumed to be in periods of horizontal lines. All other signals are determined using this as a time base.
To determine when the VCSYNC, BLANK, and SPCLK signals should become active during a frame, it
is easiest to draw them out as shown in
Figure 13 . This diagram shows the line counter along the bottom,
starting at VLinesTotal and counting down to 0. Each frame starts with the counter set to VLinesTotal. It
t
VSYNC
VCSYNC
HSYNC
Single Video Frame
t
VACTIVE
BLANK
Back Porch Interval t
VBACKPORCH
Front Porch Interval t
VFRONTPORCH
Active Video
Figure 12. HSYNC/VSYNC Video Frame