Cirrus Logic AN269 - Manual (Page 41)

AN269
AN269REV1 41
Note that VActiveStop is set such that data will never be stopped due to vertical position. Also, the SPCLK
should not be stopped due to vertical position:
VClkStart = VLinesTotal
VClkStop = VLinesTotal + 1
The blank signal is not used, but it may be desired to initialize the Vertical Blanking timing registers to a
known value:
VBlankStart = 0
VBlankStop = 0
6.4 Other Types of Framed Data Displays
The diagrams and techniques from Section 6.2 and 6.3 can easily be adapted to suite a wide variety of dis-
plays that do not fit these timings exactly. To do this, draw out the timing of the horizontal lines, carefully
noting when each synchronization signal changes. Also, note where on the line the video frame pulse (in-
dicating the first line) will make transitions. Then identity the relevant regions of time between the various
sync signals and the active region. Once identified, estimate how many VIDCLKs will be required for each
region (starting with 2 per region is a good estimate), and then calculate the required VIDCLK frequency
and period. From there, distribute the VIDCLKs to each region accordingly, and recheck to ensure that tim-
ing requirements are met. If more VIDCLKs are required for a region on the horizontal line, simply add more
for the required region and repeat the process of recalculation and distribution.
This is the same process that is used in the Frame Type 1 and Type 2 displays seen in Figures 16 and 20 .
As can be seen from those figures, change in the synchronization signals, and presence/absence of SPCLK
and data signal a change from one region to the next.
Note that in this process the vertical synchronization signal VCSYNC can only make transitions when the
horizontal line counter rolls over. This will be the point on the horizontal line where the horizontal line counter
changes from 0 to HClksTotal. This will usually determine where the remaining synchronization signals
should be placed within the line.