Cirrus Logic AN269 - Manual (Page 35)

AN269
AN269REV1 35
6.3.1 VIDCLK and Pixel Data Clock Rate
For a frame type 2 data display, the SPCLK will be gated such that clock pulses only occur during valid
data, one pulse per data set. Note that the number of pixels per SPCLK may be 1, 2, 2-2/3, 4, or 8. Also,
the number of VIDCLK periods per SPCLK may not always be constant. For example, in 2-2/3 mode,
there are 3, 2, and then 3 VIDCLKs per SPCLK (thus an average of (3+2+3 VIDCLKs/SPCLK) with (2-2/3
pixels/SPCLK) = 1 VIDCLK/pixel).
To determine the VIDCLK rate (and therefore the resulting SPCLK rate), the number of SPCLKs per hor-
izontal line must be estimated. This is done by identifying the different regions of the horizontal line, and
assigning a certain number of VIDCLKs to that region. This method is a bit complex due to the fact that
adding VIDCLKs per line will inherently increase the overall VIDCLK (and therefore SPCLK) frequency.
However, a simple iterative process can be used to determine the proper rates.
To simplify the example, we are only going to use the following timing parameters, which will later be used
as regions of time on the horizontal line (the regions will be discussed in more detail later in this chapter):
– tHSYNCH - HSYNC High pulse duration
– tVCHHSYNC - Time from VCSYNC High to HSYNC low
– tSPCLKHSYNC - Time from last SPCLK to HSYNC High on next line
– tHSYNCSPCLK - Time from HSYNC Low to first SPCLK
– tVCLHSYNC - Time from VCSYNC Low to HSync Rising Edge
– tACTIVE - The period of the actual active region itself.
The first step is to estimate the VIDCLK rate. This is done with the following formula:
DesiredVidClkFreq = {[(VIDCLKs per Pixel) * (Horizontal Resolution)] + [(2 SPCLKs for each region)*(4
regions not including the active region)]} * (Vertical Resolution) * (Desired Refresh Rate)
The quantity of VIDCLKs per Pixel (VIDCLKs per Pixel) depends on the operating mode, but is usually 1.
Note that we have estimated 2 SPCLKs for each region for each of 4 regions: HSYNC high, VCSYNC until
HSYNC, HSYNC low until first SPCLK, and last SPCLK until the next line’s HSYNC high.
The next step involves setting up the VIDCLKDIV register, and determining the actual “nearest” value of
VIDCLK frequency. This will not necessarily be the desired VIDCLK frequency, but will be close. An algo-
rithm for this is shown in
Section 3. “Generation of the Video Clock, VIDCLK” on page 2 . The value re-
turned by setting the VIDCLKDIV register is the actual frequency of VIDCLK (the quantity
ActualVidClkFreq). From the value of ActualVidClkFreq, the VIDCLK period can be determined (the quan-
tity VidClkPeriod):
VidClkPeriod = 1 / ActualVidClkFreq