Cirrus Logic AN269 - Manual (Page 18)

18 AN269REV1
AN269
6.1.1 Pixel Data Clock Rate and HClkTotal/VLinesTotal
The pixel clock rate VIDCLK can be determined from the total number of VIDCLK periods per line, total
number of horizontal lines, and the Refresh Rate.
The timing specifications for this type of display interface will usually list an HSYNC Width, Horizontal
Back Porch Width, Horizontal Front Porch Width, Horizontal Valid, Horizontal Blank length, VCSYNC
Width, VCSYNC frequency, Vertical Back Porch Width, Vertical Front Porch Width, Vertical Valid, and
Vertical Blank lengths.
A typical horizontal line for this type of display can be found in Figure 10 . This line can be divided into
regions, which are in units of VIDCLK. The total number of VIDCLK periods per line is the sum of the Hor-
izontal Valid (tHACTIVE) region, the Horizontal Front Porch region (tHFRONTPORCH), the HSYNC re-
gion (tHSYNC), and the Horizontal Back Porch region (tHBACKPORCH). The equation for this is shown
here, where tHORIZ represents the number of VIDCLK periods per horizontal line (all values are in VID-
CLK periods):
tHORIZ = tHACTIVE + tHFRONTPORCH + tHSYNC + tHBACKPORCH
Note that there may be 1, 2, 4, 8, or 2-2/3 pixels per SPCLK. This will mean that tHACTIVE is not neces-
sarily the number of horizontal pixels on the screen. Consult the datasheet of the display to determine the
number of pixels per SPCLK per horizontal line.
“Generation of the Video Clock, VIDCLK” on page 2 has
examples of the number of pixels per SPCLK (VIDCLKs/pixel is usually 1).
A typical full video frame for this type of display can be found in Figure 12 . The time spent on a single
frame is the sum of the Vertical Valid (tVACTIVE) region, the Vertical Front Porch Width (tVFRONT-
PORCH), the VCSYNC Width (tVSYNC), and the Vertical Back Porch Width (tVBACKPORCH). The
equation for this is shown here, where tVERT represents the amount of time spent per single video frame
(all time is in horizontal line periods):
tVERT = tVACTIVE + tVFRONTPORCH + tVSYNC + tVBACKPORCH
Next, the specification for the refresh rate should be determined from the datasheet. This may be speci-
fied as VCSYNC or VSYNC frequency. We will call this value fVSYNC.
Now the VIDCLK rate can be determined as a product of the above 3 values. This is shown below, where
VIDCLK refers to the VIDCLK rate (Hz):
VIDCLK = tHORIZ * tVERT * fVSYNC
To generate the proper frequency for VIDCLK, either PLL1, PLL2, or an external clock must be used. Any
of these sources may be divided down using the settings in the VidClkDiv (Video Clock Divider) register.
A simple block diagram of this divide structure and a method for determining the proper settings of
VidClkDiv can be found in
“Generation of the Video Clock, VIDCLK” on page 2 .
Once the VIDCLK rate has been determined, the horizontal and vertical alignment signals can be derived.