Cirrus Logic AN269 - Manual (Page 14)

14 AN269REV1
AN269
In the third SPCLK for 2 2/3 mode, pixel 5’s Green and Red components will be clocked out of P[1:0]. All of the Red,
Green, and Blue components of pixel 6 are clocked out of P[4:2]. Pixel 7’s Red, Green, and Blue components are
clocked out of P[7:5]. On successive SPCLK periods, the pattern of pixels will repeat.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
5
5
6
6
6
7
7
7
Pixel Data Bus
Pins P[17:0]
Pixels 5, 6 and 7 (Third SPCLK)
P
ix
e
l Da
ta
M
o
s
t S
igni
fi
c
a
n
t Bi
ts
(fr
o
m
LUT and
B
lin
k
Log
ic
)
Figure 7. 3-Bits Per Pixel Formatted as 2-2/3 Bits, Third SPCLK