Rainbow Electronics DS1876 - Manual (Page 42)

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DS1876
SFP Controller with Dual LDD Interface
Table 01h, Register F9h: RESERVED
Table 01h, Register FAh: ALARM EN 1
Table 01h, Register FBh: RESERVED
POWER-ON VALUE
READ ACCESS
N/A
WRITE ACCESS N/A
A2h AND B2h MEMORY N/A
MEMORY TYPE N/A
This register is reserved.
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
A2h AND B2h MEMORY Different A2h and B2h memory locations
MEMORY TYPE Nonvolatile (SEE)
FAh RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO
BIT 7 BIT 0
Layout is identical to ALARM 1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see
Figure 9). The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.
BITS 7:4, 2 RESERVED
BIT 3
HBAL: Enables alarm to create internal signal FETG.
0 = Disables interrupt from HBAL alarm.
1 = Enables interrupt from HBAL alarm.
BIT 1
TXP HI: Enables alarm to create internal signal FETG.
0 = Disables interrupt from TXP HI alarm.
1 = Enables interrupt from TXP HI alarm.
BIT 0
TXP LO: Enables alarm to create internal signal FETG.
0 = Disables interrupt from TXP LO alarm.
1 = Enables interrupt from TXP LO alarm.
POWER-ON VALUE
READ ACCESS
N/A
WRITE ACCESS N/A
A2h AND B2h MEMORY N/A
MEMORY TYPE N/A
This register is reserved.