National Instruments AT-MIO-16X - Manual (Page 70)

Chapter 3 Theory of Operation
AT-MIO-16X User Manual 3-4 © National Instruments Corporation
conflicts with any other equipment in your PC, you must change the
base address of the AT-MIO-16X or of the other device. See Chapter 2,
Configuration and Installation, for more information.
The PC I/O channel interface timing signals are used to generate
read-and-write signals and to define the transfer cycle size. A transfer
cycle can be either an 8-bit or a 16-bit data I/O operation. The
AT-MIO-16X returns signals to the PC I/O channel to indicate when the
board has been accessed, when the board is ready for another transfer,
and the data bit size of the current I/O transfer. Particular attention must
be paid to the AT-MIO-16X register sizes. An 8-bit access to a 16-bit
location, and vice versa, is invalid and will cause sporadic operation.
The interrupt control circuitry routes any enabled board-level interrupt
requests to the selected interrupt request line. The interrupt requests are
tristate output signals which allow the AT-MIO-16X board to share the
interrupt line with other devices. Eight interrupt request lines are
available for use by the AT-MIO-16X: IRQ3, IRQ4, IRQ5, IRQ7,
IRQ10, IRQ11, IRQ12, and IRQ15. These interrupt levels are selectable
from one of the registers in the AT-MIO-16X register set. Six different
interrupts can be generated by the AT-MIO-16X. Each of the following
cases is individually enabled and cleared:
• When the ADC FIFO buffer is ready to be serviced
• When a data acquisition operation completes (including an
OVERFLOW or OVERRUN error)
• When a DMA terminal count pulse is received on DMA Channel A
or DMA Channel B
• When the DAC FIFO buffer is ready to be serviced
• When a DAC sequence completes (including an UNDERFLOW
error)
• When a falling edge signal is detected on the DAC update signal
(internal or external)
The DMA control circuitry generates DMA requests whenever an A/D
measurement is available from the ADC FIFO and when the DAC FIFO
is ready to receive more data. The DMA circuitry supports full PC I/O
channel 16-bit DMA transfers. DMA Channels 5, 6, and 7 of the PC I/O
channel are available for such transfers. DMA Channels 0, 1, 2, and 3
are available for 16-bit transfers on EISA computers only, and not on
PC AT and compatible computers. With the DMA circuitry, either
single-channel transfer mode or dual-channel transfer mode can be