National Instruments AT-MIO-16X User Manual

Page 329

Index

AT-MIO-16X User Manual

I-20

programmed cycle waveform

generation, 5-30

pulsed cyclic waveform generation, 5-32

STARTDAQ Register, 3-28
Status Register 1

description, 4-25 to 4-29
servicing update requests, 5-36

Status Register 2, 4-30
storage environment specifications, A-9
straight binary mode A/D conversion values

(table), 4-33

switch settings. See base I/O address selection.
system noise, A-4

technical support, D-1 to D-2
telephone and fax support, D-2
theory of operation

analog input circuitry, 3-6 to 3-8

A/D converter, 3-6
ADC FIFO buffer, 3-7
block diagram, 3-5
input multiplexers, 3-6
PGIA, 3-7

analog output circuitry, 3-15 to 3-18

block diagram, 3-16
calibration, 3-17 to 3-18
circuitry, 3-16 to 3-17
configuration, 3-17

AT-MIO-16X block diagram, 3-1
DAC waveform circuitry and timing,

3-18 to 3-24

FIFO continuous cyclic waveform

generation, 3-22 to 3-23

FIFO programmed cyclic waveform

generation, 3-23

FIFO pulsed waveform generation,

3-23 to 3-24

waveform circuitry, 3-18 to 3-20

waveform timing circuitry,

3-20 to 3-22

data acquisition timing circuitry,

3-8 to 3-12

block diagram, 3-5
data acquisition rates, 3-15
multiple-channel data acquisition,

3-12 to 3-15

single-channel data acquisition,

3-9 to 3-12

single-read timing, 3-8 to 3-9

digital I/O circuitry, 3-24 to 3-25
functional overview, 3-1 to 3-2
PC I/O channel interface circuitry,

3-2 to 3-5

RTSI bus interface circuitry, 3-29 to 3-30
timing I/O circuitry, 3-25 to 3-29

time-lapse measurements, 2-38
timing circuitry. See data acquisition timing

circuitry; timing I/O circuitry.

timing connections, 2-33 to 2-42

counter signal connections, 2-37 to 2-42
EXTCONVERT* signal, 2-34
EXTGATE* signal, 2-36
EXTSTROBE* signal, 2-33
EXTTMRTRIG* signal, 2-36
EXTTRIG* signal, 2-35
SCANCLK signal, 2-33

timing I/O

overview, 1-3
specifications, A-8

timing I/O circuitry, 3-25 to 3-29

block diagram, 3-26
counter block diagram, 3-27

timing signals, PC I/O channel interface, 3-4
TMRREQ bit

clearing analog output circuitry, 5-32
description, 4-27 to 4-28
interrupt programming, 5-43
servicing update requests, 5-35