Sundance SMT381 2004 - Manual (Page 4)

Table of Contents
1 Introduction ...........................................................................................................10
1.1 Overview ........................................................................................................10
1.2 Module Features.............................................................................................10
1.3 Possible Applications......................................................................................10
1.4 Related Documents ........................................................................................11
2 Functional Description...........................................................................................12
2.1 Module Overview............................................................................................12
2.2 Communication Ports (ComPorts) ..................................................................13
2.3 Sundance High-Speed Bus (SHB) ..................................................................13
2.4 Main Analogue characteristics ........................................................................14
2.5 Data stream description..................................................................................14
2.5.1 Description of internal FPGA blocks ............................................................15
2.6 Clock Structure...............................................................................................17
2.7 Trigger Structure.............................................................................................18
2.8 Power Supply and Reset Structure.................................................................19
2.9 MSP430 Functionality.....................................................................................20
2.10 FPGA Configuration......................................................................................22
2.11 Analogue output section ...............................................................................22
2.12 DAC Settings................................................................................................24
3 Description of interfaces........................................................................................24
3.1 DAC Control Interface.....................................................................................24
3.2 DAC Data Interface ........................................................................................25
3.3 Memory Interface............................................................................................25
3.4 MSP430 Interface...........................................................................................25
3.5 Serial Number ................................................................................................25
3.6 PLL Interface ..................................................................................................25
3.7 Clock Synthesizer Interface ............................................................................26
3.8 TIM Interface ..................................................................................................26
3.9 External Trigger ..............................................................................................26
3.10 Daughter card Interface ................................................................................26
3.11 RSL Interface (RSL not yet available) ...........................................................33
3.11.1 RSL Connector and Pinout Definition .....................................................33
3.11.2 RSL Cable Definition ..............................................................................35
3.12 SHB Interface ...............................................................................................35
4 Firmware Description ............................................................................................39
4.1 Main States ....................................................................................................39
4.2 Configuring the FPGA.....................................................................................40
4.3 Setting up the FPGA.......................................................................................40
5 Control Register Settings ......................................................................................41
5.1 Control Packet Structure.................................................................................41
5.2 Reading and Writing Registers .......................................................................42
5.3 Memory Map ..................................................................................................43
5.4 Register Descriptions......................................................................................45