Sundance SMT381 2004 - Manual (Page 14)

2.4 Main Analogue characteristics
The main analogue characteristics are listed in the following table:
Analogue outputs
Output current range 20mA
Data Format Analogue current
External sampling clock inputs (The clock frequency is divided by 2 on the SMT381 for a DDR clock for the DAC)
LVPECL Clock
Signal format LVPECL
Frequency range 25MHz to 1000 MHz
RF Clock
Signal format Sinus wave
Frequency range 25MHz to 1000 MHz
Amplitude 0dBm Typ
External trigger inputs
Signal format LVPECL
Frequency range DC to 100 MHz
ADC Performance @ Single tone at -1dBFS, 800MSa/s, DC to 400MHz (From DAC datasheet)
Spurious Free Dynamic Range (SFDR) @ 20MHz
75dBc
Spurious Free Dynamic Range (SFDR) @ 300MHz
58dBc
Cross-talk 4 tone test, each tone at -15dBFS, centred at 276MHz
67dBc
Table 1. Main analogue characteristics of the SMT381.
2.5 Data stream description
The data paths for both channels on the module are the same. The DAC is driven by
a single clock either generated on the module or provided by the user through an
MMBX connector. As only a single clock is present on the module the two data-paths
will always be in exact synchronization. As the data path on this module finds its
origin in the SMT338-VP’s FPGA the internal data path of the FPGA must also be
explained. Figure 2 shows the SMT338-VP’s FPGA data path.