Sundance SMT381 2004 - Manual (Page 16)

Memory Interface
The memory interface block is the DDR SDRAM controller. This block is responsible
to all write and read transactions to and from the DDR SDRAM.
Retrieve from Memory
The retrieve from memory block retrieves stored data in the DDR SDRAM when it
receives a valid read command. The read command specifies the location and
amount of data that needs to be retrieved.
SHB Interface
The data received from the SHB interface is stored in memory. The SHB interface
controls the SHB bus between the SMT338-VP and any module connected to the
SHB sending the data.
In addition to the above interface blocks the FPGA also implements the following
functions (not indicated on the diagram):
Trigger Interface
Handles all triggers. Triggers may be received from the external hardware trigger
connectors (two separate triggers – one for each channel), or by receiving a trigger
command over the ComPort (also separate commands for each channel). When a
trigger is received data is sent to the SMT381 from the memory on the SMT338-VP.
DAC Control Interface
Control interface for writing setup information to the DAC on the SMT381 to configure
it for any selected mode of operation. Data is received over the ComPort interface
and written out to the DAC over a serial interface.
Clock Synthesizer Interface
Control interface for writing setup information to the clock synthesizer on the SMT381
to configure its clock output frequency. Data is received over the ComPort interface
and written out to the clock synthesizer over a serial interface.
PLL Interface
Control interface for writing setup information to the PLL on the SMT381 to configure
the VCO output voltage. Data is received over the ComPort interface and written out
to the PLL over a serial interface. The PLL drives one VCO circuit. This VCO + PLL
circuit generates the main system clock and is configurable between 600 and 1200
MHz. The side is called the RF side. This clock is then divided by two which enables
the DAC to have a very stable PLL + VCO clock ranging from 300 to 600MHz.
DAC Interface
The DAC interface sends a high speed data stream from the FPGA to the DAC
present on the SMT381. There are two channels available on the DAC and data is
latched into the DAC on the rising and falling edge (DDR) of the DAC’s input clock
which is clocked into the FPGA to make data synchronization easier. The inputs are
14bit data streams which is clocked out of the FPGA at a maximum frequency of
420MHz (on both edges, thus 840MSPS).