Sundance SMT381 2004 - Manual (Page 25)

Note 1: The serial interface on the DAC side uses 1.8V signalling levels. These
control lines are however connected unto a 3.3V bank on the FPGA with additional
pull-up resistors on the SMT381 to 1.8V. For this reason the FPGA firmware may
never drive ‘1’ out on these pins as it will drive the DAC at 3.3V and thus damage it.
The firmware may only drive ‘0’ for ‘0’ and ‘Z’ for ‘1’. Because of the pull-up resistor
the ‘Z’ will be pulled up to 1.8V. This approach works well and any used wishing to
develop his own firmware is advised to take a look at the SMT381 example firmware
before developing his own.
3.2 DAC Data Interface
The output of each channel from the SMT338-VP to the DAC is a 14 bit LVDS data
bus clocked on the synchronized DAC clock.
Note 1: The data bus between the FPGA and the DAC is wired in a strange way to
assist routing. If a user wants to develop his own VHDL design and not use the
example design he is advised to take a look at the wiring of the example design to
assist him with his own design.
Note 2: On Rev 01 of the SMT381 the positive and negative data pairs of the LVDS
bus between the FPGA and the DAC is swapped for one of the two channels. This
results in a data flip. This issue is corrected in firmware by inverting the data before
writing it out over the interface. Once again any user wanting to do his own design is
advised to take a look at the example firmware design.
3.3 Memory Interface
Two groups of two 16 bit Micron DDR SDRAMs form the volatile sample storage
space of the module. Each DDR SDRAM is 256 MBits in size. This provides the
module with a total of 64Mbytes (or 32 Mega samples) of storage space per channel.
Each channel contains a 32 bit DDR SDRAM controller. This interface is capable of
data transfer at 1 GBytes / s. It is thus fast enough to write the outgoing DAC data
stream.
3.4 MSP430 Interface
After configuration the microprocessor communicates with the FPGA using the IO
pins of the FPGA Slave Select Configuration interface. The MSP is the master of the
interface and will continually write the serial number and the measured on-board
voltages to the FPGA. A system host can then read this data from the FPGA over the
ComPort interface.
3.5 Serial Number
A Maxim 1-Wire silicon serial number device is located on the SMT381 and the
SMT338-VP. This is used to assign a unique serial number to each module.
3.6 PLL Interface
A three wire uni-directional control interface is implemented between the FPGA and
the PLL on the daughter card. This PLL sets and controls the voltage for the VCO
that generates the main clock.