Sundance SMT381 2004 - Manual (Page 18)

The second clock source is a voltage controlled oscillator with a phase lock loop.
This combination has a very stable output. However a limited frequency range can be
attained by this combination (300MHz – 600MHz). This is achieved by taking a
600MHz -1200MHz VCO and dividing the output by 2. The output clock must also be
scaled to LVPECL.
Alternatively the user can provide the module with an external LVPECL clock or an
external RF clock. The user can select between any of these input clocks.
The selected clock then drives the DAC and is also distributed to the main module
(SMT338-VP) for data synchronization purposes. On the FPGA of the SMT338-VP a
PLL synchronizes the clock with the data being sent by using the supplied clock and
looping that same clock to the DAC and back. This technique synchronizes the clock
to the data is being sent out on (SMT338-VP side) even further with the clock used in
the DAC. Synchronization issues become a bigger factor as the clock frequencies get
bigger.
All the clock control is done on the SMT338-VP side in firmware on the FPGA. The
multiplexer selects the clock and this clock is then used inside the DAC and SMT338-
VP for data transmitting purposes. The set up of the clock packages is also done in
firmware.
Finally an external trigger is supplied to the SMT338-VP and the multiplexed clock
divided by 8. The trigger can be used for memory storing and retrieving functions etc.
while the clock divided by 8 is mainly for debugging purposes.
2.7 Trigger Structure
There are two main data-paths (per channel) for data received either from RSL
interface (not yet implemented) or SHB/memory interface. The first data path is
directly connected to the DAC interface and sends the data as is. The second data
path is either a direct link to the DAC interface or to memory. The trigger settings
differ depending on the path used.
There are two main sources for the trigger. The first is an LVPECL trigger received
over the MMBX connector (triggered on rising edge). The second is a trigger
command. The trigger command can be received either over the RSL interface or via
the ComPorts.
The following trigger settings are possible for the RSL interface (RSL not yet
implemented):
•
Start transmitting data when a trigger is received. Stop transmitting when the
next trigger is received.
•
Transmit a pre-determined amount of samples when a trigger is received.
•
Ignore all triggers and transmit data continuously (cycle through memory).
The following trigger settings are possible for the DDR SDRAM data-path: