BECKHOFF EtherCAT Registers Section II - Manual (Page 47)

PDI Configuration (0x0150:0x0153)
Slave Controller – Register Description II-35
3.28.6 PDI On-chip bus configuration
Table 43: Register PDI On-chip bus configuration (0x0150)
ESC20 ET1100 ET1200 IP Core
Bit Description ECAT PDI Reset Value
4:0 On-chip bus clock:
0: asynchronous
1-31: synchronous multiplication factor
(N * 25 MHz)
r/- r/- IP Core: Depends on
configuration
7:5 On-chip bus:
000:
Altera
®
Avalon
®
001: AXI
®
010: Xilinx
®
PLB v4.6
100: Xilinx OPB
others: reserved
r/- r/-
Table Register Sync/Latch[1:0] PDI Configuration (0x0151) moved to chapter 3.28.7
Table 44: Register PDI On-chip bus extended configuration (0x0152:0x0153)
ESC20 ET1100 ET1200 IP Core
V1.1.1/
V2.00a
Bit Description ECAT PDI Reset Value
1:0 Read prefetch size (in cycles of PDI width):
0:
4 cycles
1: 1 cycles (typical)
2: 2 cycles
3: Reserved
r/- r/- IP Core: Depends on
configuration
7:2 Reserved r/- r/-
10:8 On-chip bus sub-type for AXI:
000:
AXI3
001: AXI4
010: AXI4 LITE
others: reserved
r/- r/-
15:11 Reserved r/- r/-