BECKHOFF EtherCAT Registers Section II - Manual (Page 4)

DOCUMENT HISTORY
II-IV Slave Controller – Register Description
Version Comment
1.6

EEPROM Control/Status register (0x0502:0x0503): Error bit description clarified

EEPROM Interface and MII Management Interface: access to special registers
is blocked while interface is busy

EEPROM Interface: EEPROM emulation by PDI added

Extended IP Core features (0x0F80:0x0FFF): reset values moved to Section III

Reset values of DC Receive Time registers are undefined

MI Control/Status register bit 0x510.7 is read only

FMMUs supported (0x0004): ET1200 has 3 FMMUs, not 4

AL Event Request register: SyncManager changed flag (0x220.4) is not
available in IP Core versions before and including 1.1.1/1.01b

Configured Station Alias (0x0012:0x0013) is only taken over at first EEPROM
load after power-on or reset

Moved available PDIs depending on ESC to Section I

SyncManager PDI Control (0x807 etc.): difference between read and write
access described

General Purpose I/O registers (0x0F10:0x0F1F) width variable (1/2/4/8 Byte)

MII Management Interface enhancement: link detection and assignment to PDI
added

Write access to DC Time Loop Control unit by PDI configurable for IP Core
(V2.0.0/2.00a)

Editorial changes
1.7

MII Management Control/Status (0x0510) updated: PHY address offset is 5 bits,
feature bits have moved

System time register (0x0910:0x0917): clarified functionality

Process Data RAM (0x1000 ff.): accessible only if EEPROM is loaded

Digital I/O extended configuration (0x0152:0x0153): Set to 0 in bidirectional
mode

Editorial changes
1.8

DC register accessibility depends on DC power saving settings in PDI Control
register (0x0140[11:10])

AL Event Request register (0x0220): AL Control Event (Bit 0) is cleared by
reading AL Control register (0x0120), not AL Event Request register

EEPROM Control/Status register bit 0x0502.12 renamed to EEPROM loading
status

Description of Push-Pull/Open-Drain output drivers for SPI, µController, and
SYNC0/1 enhanced

Speed Counter Start register (0x0930:0x0931): Write access resets calculated
Time Loop Control values

Speed Counter Diff register (0x0932:0x0933): Deviation calculation added

DC Start Time Cyclic operation (0x0990:0x0997) and Next Sync1 Pulse
(0x0998:0x099F) relate to the System time

Reset DC Control loop (write 0x0930:0x0931) after changing filter depths
(0x0934 or 0x0935)

Editorial changes
1.9

Update to EtherCAT IP Core Release 2.2.0/2.02a

Register availability added

Writing to DC Filter Depth registers 0x0934:0x0935 resets filters

DC Activation register (0x0981) enhanced

DC Activation state register (0x0984) added

Reserved registers or register bits: write 0, ignore read values

Enhanced link detection 0x0140.9 has compatibility issues with EBUS ports, not
MII ports

Port dependent Enhanced link detection (0x0140[15:12] added

PHY Port y Status bit 5 added (port configuration updated)

ESC10 removed

Editorial changes