BECKHOFF EtherCAT Registers Section II - Manual (Page 10)

TABLES
II-X Slave Controller – Register Description
Table 61: Register Watchdog Counter Process Data (0x0442) ............................................................ 45
Table 62: Register Watchdog Counter PDI (0x0443) ............................................................................ 45
Table 63: SII EEPROM Interface Register overview ............................................................................. 46
Table 64: Register EEPROM Configuration (0x0500) ........................................................................... 46
Table 65: Register EEPROM PDI Access State (0x0501) .................................................................... 46
Table 66: Register EEPROM Control/Status (0x0502:0x0503) ............................................................ 47
Table 67: Register EEPROM Address (0x0504:0x0507) ...................................................................... 48
Table 68: Register EEPROM Data (0x0508:0x050F [0x0508:0x050B]) ............................................... 48
Table 69: Register EEPROM Data for EEPROM Emulation Reload IP Core (0x0508:0x050F) ........... 49
Table 70: MII Management Interface Register Overview ...................................................................... 50
Table 71: Register MII Management Control/Status (0x0510:0x0511) ................................................. 51
Table 72: Register PHY Address (0x0512) ........................................................................................... 52
Table 73: Register PHY Register Address (0x0513) ............................................................................. 52
Table 74: Register PHY Data (0x0514:0x0515) .................................................................................... 52
Table 75: Register MII Management ECAT Access State (0x0516) ..................................................... 52
Table 76: Register MII Management PDI Access State (0x0517) ......................................................... 53
Table 77: Register PHY Port y (port number y=0 to 3) Status (0x0518+y) ........................................... 53
Table 78: FMMU Register overview ...................................................................................................... 54
Table 79: Register Logical Start address FMMU y (0x06y0:0x06y3) .................................................... 54
Table 80: Register Length FMMU y (0x06y4:0x06y5) ........................................................................... 54
Table 81: Register Start bit FMMU y in logical address space (0x06y6) .............................................. 54
Table 82: Register Stop bit FMMU y in logical address space (0x06y7) .............................................. 54
Table 83: Register Physical Start address FMMU y (0x06y8-0x06y9).................................................. 55
Table 84: Register Physical Start bit FMMU y (0x06yA) ....................................................................... 55
Table 85: Register Type FMMU y (0x06yB) .......................................................................................... 55
Table 86: Register Activate FMMU y (0x06yC) ..................................................................................... 55
Table 87: Register Reserved FMMU y (0x06yD:0x06yF) ..................................................................... 55
Table 88: SyncManager Register overview ........................................................................................... 56
Table 89: Register physical Start Address SyncManager y (0x0800+y*8:0x0801+y*8) ....................... 56
Table 90: Register Length SyncManager y (0x0802+y*8:0x0803+y*8) ................................................ 56
Table 91: Register Control Register SyncManager y (0x0804+y*8) ..................................................... 57
Table 92: Register Status Register SyncManager y (0x0805+y*8) ....................................................... 58
Table 93: Register Activate SyncManager y (0x0806+y*8) .................................................................. 59
Table 94: Register PDI Control SyncManager y (0x0807+y*8) ............................................................. 60
Table 95: Register Receive Time Port 0 (0x0900:0x0903) ................................................................... 61
Table 96: Register Receive Time Port 1 (0x0904:0x0907) ................................................................... 61
Table 97: Register Receive Time Port 2 (0x0908:0x090B) ................................................................... 61
Table 98: Register Receive Time Port 3 (0x090C:0x090F) .................................................................. 62
Table 99: Register Receive Time ECAT Processing Unit (0x0918:0x091F) ......................................... 62
Table 100: Register System Time (0x0910:0x0913 [0x0910:0x0917]) ................................................. 63
Table 101: Register System Time Offset (0x0920:0x0923 [0x0920:0x0927]) ...................................... 63
Table 102: Register System Time Delay (0x0928:0x092B) .................................................................. 64
Table 103: Register System Time Difference (0x092C:0x092F) ........................................................... 64
Table 104: Register Speed Counter Start (0x0930:0x931) ................................................................... 64
Table 105: Register Speed Counter Diff (0x0932:0x933) ..................................................................... 64
Table 106: Register System Time Difference Filter Depth (0x0934)..................................................... 65
Table 107: Register Speed Counter Filter Depth (0x0935) ................................................................... 65
Table 108: Register Receive Time Latch Mode (0x0936) ..................................................................... 66
Table 109: Register Cyclic Unit Control (0x0980) ................................................................................. 67
Table 110: Register Activation register (0x0981) .................................................................................. 68
Table 111: Register Pulse Length of SyncSignals (0x0982:0x983) ...................................................... 68
Table 112: Register Activation Status (0x0984) .................................................................................... 69
Table 113: Register SYNC0 Status (0x098E) ....................................................................................... 69
Table 114: Register SYNC1 Status (0x098F) ....................................................................................... 69
Table 115: Register Start Time Cyclic Operation (0x0990:0x0993 [0x0990:0x0997]) .......................... 70
Table 116: Register Next SYNC1 Pulse (0x0998:0x099B [0x0998:0x099F]) ....................................... 70
Table 117: Register SYNC0 Cycle Time (0x09A0:0x09A3) .................................................................. 70
Table 118: Register SYNC1 Cycle Time (0x09A4:0x09A7) .................................................................. 70
Table 119: Register Latch0 Control (0x09A8) ....................................................................................... 71
Table 120: Register Latch1 Control (0x09A9) ....................................................................................... 71
Table 121: Register Latch0 Status (0x09AE) ........................................................................................ 72
Table 122: Register Latch1 Status (0x09AF) ........................................................................................ 72