BECKHOFF EtherCAT Registers Section II - Manual (Page 3)

DOCUMENT HISTORY
Slave Controller – Register Description II-III
DOCUMENT HISTORY
Version Comment
1.0 Initial release
1.1

Latch0/1 state register bit 0x09AE.2 and 0x09AF.2 added (ET1100 and IP
Core)

On-chip Bus configuration for Avalon
®
: Extended PDI configuration register
0x0152[1:0] added
1.2

On-chip Bus configuration: Extended PDI configuration register 0x0152[1:0]
now valid for both Avalon and OPB

ESC DL Status: PDI Watchdog Status constantly 1 for ESC10

EEPROM Control/Status: Selected EEPROM Algorithm not readable for
ESC10/20
1.3

EEPROM/MII Management Interface: Added self-clearing feature of command
register

SPI extended configuration (0x0152:0x0153): Reset Value is EEPROM ADR
0x0003, not 0x0001

ESC DL Control (0x0100.0): Added details about Source MAC address change

Power-On Values ET1100 (0x0E000): P_CONF does not correspond with
physical ports
1.4

Sync/Latch PDI configuration register: Latch configuration clarified

AL Control register: mailbox behavior described

Editorial changes
1.5

ESC DL Control (0x0100:0x0103): FIFO Size description enhanced

IP Core: Extended Features (reset value of User RAM 0x0F80:0x0FFF) added

MII Management Interface: Write access by PDI is only possible for ET1100 if
Transparent Mode is enabled. Corrected register read/write descriptions.

MII Management Control/Status register (0x0510:0x0511): Error bit description
clarified. Write Enable bit is self-clearing.

ESC DL Control (0x0100:0x0103): Temporary setting DL not available for
ESC10/20

EEPROM PDI Access State register (0x0501): write access depends on
EEPROM configuration

EEPROM Control/Status register (0x0502:0x0503): Error bit description
clarified. Write Enable bit is self-clearing.

Registers initialized from EEPROM have Reset value 0, and EEPROM value
after EEPROM was loaded successful

AL Event Request (0x0220:0x0223) description clarified: SyncManager
configuration changed interrupt indicates activation register changes.

DC Latch0/1 Status (0x09AE:0x09AF): Event flags are only available in Single
event mode

DC SYNC0 Cycle Time (0x09A0:0x09A3): Value of 0 selects single pulse
generation

64 Bit Receive Time ECAT Processing Unit (0x0918:0x091F) is also available
for 32 Bit DCs. Renamed register to Receive Time ECAT Processing Unit

RAM Size (0x0006) ET1200: 1 Kbyte

Editorial changes