Artesyn MVME8100/MVME8110 Installation and Use (September 2014) - Manual (Page 76)

Functional Description
MVME8100 / MVME8110 Installation and Use (6806800P25G) 76
The OS Watchdog (OSWD) is used to guard loading of the operating system. The OS has to service OSWD
before timeout or OSWD will request a hard reset sequence to reset the board.
The configuration switch S2-1 is used to enable or disable both watchdogs. By default, the watchdogs are
disabled.
4.5.3.1 Initial Hardware Watchdog
Initial Hardware Watchdog (IWD) starts after reset deassertion. This watchdog has to be serviced within 8s
after a reset deassertion, otherwise a IWD reset will be requested.
The Initial Hardware Watchdog is serviced by writing 0xEEA1 to CPLD Command/Status Register.
4.5.3.2 OS Watchdog
The OS Watchdog (OSWD) is not armed after reset. It is enabled right after the IWD is disabled. The OSWD
timeout is set to 108s. If the timer terminates, the OSWD reset sequence will be initiated.
OSWD is serviced and disabled by writing 0xBBC2 to CPLD Command/Status Register.
4.5.4 CPLD Tick Timer
The MVME8100 is designed to provide three independent 32-bit timers. These timers are implemented in
the CPLD which provides the fully programmable registers required for these timers.
4.6 Ethernet Interfaces
The P5020 / P5010 has five dTSEC controllers. The controllers can be configured to implement RGMII, GMII,
or SGMII interfaces to external Ethernet transceivers.
If IWD is not serviced after switching over to the SPI1 U-Boot Flash, board will infinitely try to
boot to SPI1 U-Boot Flash.
By default, U-Boot will disable both the IWD and the OSWD.