Fifo ip core references, Fifo ip core references -1 – Altera MAX 10 Embedded Memory User Manual
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FIFO IP Core References
9
2015.05.04
UG-M10MEMORY
The FIFO IP core implements the FIFO mode, enabling you to use the memory blocks as FIFO buffers.
• Use the FIFO IP core in single clock FIFO (SCFIFO) and dual clock FIFO (DCFIFO) modes to
implement single- and dual-clock FIFO buffers in your design.
• Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock
domain.
• The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.
Figure 9-1: FIFO IP Core: SCFIFO Mode Signals
data[]
wrreq
rdreq
q[]
full
almost_full
clock
empty
almost_empty
usedw[]
sclr
aclr
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