Altera MAX 10 Embedded Memory User Manual
Page 27
Parameter
Values
Description
Create one clock enable signal for each
clock signal.
On/Off
Specifies whether to turn on the option
to create one clock enable signal for
each clock signal.
More Options
Use clock
enable for port
A input
registers
On/Off
Specify whether to use clock enable for
port A input and output registers.
Use clock
enable for port
A output
registers
On/Off
Specify whether to use clock enable for
port A input and output registers.
Create an
'addressstall_a'
input port
On/Off
Specifies whether to create clock
enables for address registers. You can
create these ports to act as an extra
active low clock enable input for the
address registers.
Create an ‘aclr’ asynchronous clear for the
registered ports.
On/Off
Specifies whether to create an
asynchronous clear port for the
registered ports.
More Options
'q' port
On/Off
Specifies whether the
q
port is cleared
by the
aclr
port.
Create a 'rden' read enable signal
On/Off
Specifies whether to create a
rden
read
enable signal.
Parameter Settings: Read During Write Option
Single Port Read During Write Option
What should the q output be when
reading from a memory location being
written to?
• Don't Care
• New Data
• Old Data
Specifies the output behavior when
read-during-write occurs.
• Don't Care—The RAM outputs
"don't care" or "unknown" values
for read-during-write operation.
• New Data—New data is available
on the rising edge of the same clock
cycle on which it was written.
• Old Data— The RAM outputs
reflect the old data at that address
before the write operation
proceeds.
Get x's for write masked bytes instead of
old data when byte enable is used
On/Off
Turn on this option to obtain 'X' on
the masked byte.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
UG-M10MEMORY
2015.05.04
RAM: 1-Port IP Core Parameters For MAX 10 Devices
4-5
RAM: 1-Port IP Core References
Altera Corporation