Altera MAX 10 Embedded Memory - Manual (Page 11)

Related Information
• Internal Memory (RAM and ROM) User Guide.
Resetting Registers in M9K Blocks
There are three ways to reset registers in the M9K blocks:
• Power up the device
• Use the
aclr
signal for output register only
• Assert the device-wide reset signal using the DEV_CLRn option
MAX 10 Embedded Memory Operation Modes
The M9K memory blocks allow you to implement fully-synchronous SRAM memory in multiple
operation modes. The M9K memory blocks do not support asynchronous (unregistered) memory inputs.
Note: Violating the setup or hold time on the M9K memory block input registers may corrupt memory
contents. This applies to both read and write operations.
Supported Memory Operation Modes
Table 2-2: Supported Memory Operation Modes in the M9K Embedded Memory Blocks
Memory Operation Mode Related IP Core Description
Single-port RAM RAM: 1-PORT IP Core
Single-port mode supports non-simultaneous read
and write operations from a single address.
Use the read enable port to control the RAM output
ports behavior during a write operation:
• To show either the new data being written or the
old data at that address, activate the read enable
during a write operation.
• To retain the previous values that are held
during the most recent active read enable,
perform the write operation with the read enable
port deasserted.
Simple dual-port RAM RAM: 2-PORT IP Core
You can simultaneously perform one read and one
write operations to different locations where the
write operation happens on port A and the read
operation happens on port B.
True dual-port RAM RAM: 2-PORT IP Core
You can perform any combination of two port
operations:
• two reads, two writes, or,
• one read and one write at two different clock
frequencies.
UG-M10MEMORY
2015.05.04
Resetting Registers in M9K Blocks 2-7
MAX 10 Embedded Memory Architecture and Features Altera Corporation
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